Selective die electrical insulation by additive process

• US 9,490,230 B2
• Filed: 09/28/2015
• Issued: 11/08/2016
• Est. Priority Date: 10/27/2009
• Status: Active Grant

• Current Assignee: Invensas Corporation
• Original Assignee: Invensas Corporation
• Inventors: Leal, Jeffrey S.
• Primary Examiner(s): Lebentritt, Michael
• Assistant Examiner(s): DEHNE, AARON A
• Application Number:
  US14/868,090
• Publication Number:
  US 20160020188A1
• Time in Patent Office: 407 Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/02282 liquid deposition, e.g. spin-coating, sol-gel techniques, spray coating
• CPC Class Codes: H01L 21/02288 printing, e.g. ink-jet printing per se B41J
• CPC Class Codes: H01L 21/31 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques encapsulating layers H01L21/56; After treatment of these layers; Selection of materials for these layers
• CPC Class Codes: H01L 21/324 Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering H01L21/20 - H01L21/288 and H01L21/302 - H01L21/322 take precedence
• CPC Class Codes: H01L 21/56 Encapsulations, e.g. encapsulation layers, coatings
• CPC Class Codes: H01L 21/76801 characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
• CPC Class Codes: H01L 21/76828 thermal treatment
• CPC Class Codes: H01L 2224/19 Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 2224/24145 the bodies being stacked
• CPC Class Codes: H01L 2224/76155 Jetting means, e.g. ink jet
• CPC Class Codes: H01L 2224/82051 Forming additional members
• CPC Class Codes: H01L 2224/82101 by additive methods, e.g. direct writing
• CPC Class Codes: H01L 2224/82102 using jetting, e.g. ink jet
• CPC Class Codes: H01L 2224/82355 having an external coating, e.g. protective bond-through coating
• CPC Class Codes: H01L 2225/06524 Electrical connections formed on device or on substrate, e.g. a deposited or grown layer
• CPC Class Codes: H01L 2225/06551 Conductive connections on the side of the device
• CPC Class Codes: H01L 2225/06562 at least one device in the stack being rotated or offset
• CPC Class Codes: H01L 24/19 Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/24 of an individual high density interconnect connector
• CPC Class Codes: H01L 24/25 of a plurality of high density interconnect connectors
• CPC Class Codes: H01L 24/82 : by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] interconnection structure between a plurality of semiconductor chips H01L23/5389
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01056 : Barium [Ba]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/14 : Integrated circuits

Abstract

Additive processes are employed for electrically insulating selected surface regions on a stack of die; and methods for electrically interconnecting die in a stack of die, include additive processes for electrically insulating selected surface regions of the die. Regions that are not insulated according to the invention are available for electrical connection using electrically conductive material applied in flowable form to make electrically conductive traces.

Claims

1. A method for forming a stacked die assembly, comprising:

on a plurality of die, electrically insulating a selected interconnect pad of a plurality of interconnect pads exposed at a selected region of a die by selectively applying a dielectric material onto the selected interconnect pad in the selected region of the die by selectively depositing at least one of a spot or a line of dielectric material via a nozzle onto the selected region of the die, the selectively depositing leaving nonselected interconnect pads exposed and free from depositing of the dielectric material thereon, such that the nonselected interconnect pads are available for electrical interconnection without requiring the deposited dielectric material to be removed from the nonselected interconnect pads, the nozzle being controlled so that the dielectric material flows from the nozzle during intervals when a flow axis of the nozzle is directed at the selected interconnect pad and does not flow from the nozzle during intervals when the flow axis is directed at an unselected interconnect pad; and

stacking the plurality of die such that front sides of the die are arranged in a plurality of parallel planes, wherein at least some of the interconnect pads are aligned in respective columns extending transverse to the parallel planes,

wherein in the stacked die assembly, at least one nonselected interconnect pad in a column is available for electrical interconnection and the selected interconnect pads in the same column are electrically insulated.

2. The method of claim 1 wherein the selected region of the die includes a selected region of a die sidewall, comprising selectively applying the dielectric material onto the selected region of the die sidewall surface.

3. The method of claim 1 wherein the selected region of the die includes a selected area of the front side of the die, comprising selectively applying the dielectric material onto the selected area of the front side of the die.

4. The method of claim 1 wherein the selected region of the die includes a selected area inboard of an interconnect pad, comprising selectively applying the dielectric material onto the selected area inboard of the interconnect pad.

5. The method of claim 1 wherein the selected region of the die includes a selected area of an interconnect margin of the die, comprising selectively applying the dielectric material onto the selected area of the interconnect margin.

6. The method of claim 1 wherein the selected region of the die includes a selected area adjacent an interconnect edge of the die, comprising selectively applying the dielectric material onto the selected area adjacent the interconnect edge.

7. The method of claim 1 wherein the selected region of the die includes a selected area between interconnect pads in a row of pads on the die, comprising selectively applying the dielectric material onto the selected area between interconnect pads.

8. The method of claim 1, further comprising forming a conformal electrically conductive trace contacting a nonselected interconnect pad and passing over an insulating region resulting from selectively applying the dielectric material over the selected region.

9. The method of claim 8 wherein forming the electrically conductive trace comprises depositing an electrically conductive material in flowable form and subsequently curing the material to form the trace.

10. The method of claim 8 wherein the dielectric material is characterized by having a surface at least partly nonwettable by the electrically conductive material.

11. The method of claim 8, further comprising treating the deposited dielectric material so that a surface thereof is at least partly nonwettable by the electrically conductive material.

12. The method of claim 1 wherein applying the dielectric material includes directing an aerosolized electrically insulative material onto the selected region.

13. The method of claim 1 wherein applying the dielectric material includes directing a curable electrically insulative material onto the selected region, further comprising curing the material.

16. The method of claim 1, wherein the stacking is performed prior to the electrically insulating the die.

14. A method for forming a stacked die assembly, comprising providing semiconductor die having electrical interconnect pads arranged in an interconnect margin adjacent an interconnect die edge;

stacking a plurality of said die such that front sides of the die are arranged in parallel planes, and such that the pads in successive die in the stack are arranged in a plurality of columns each extending transverse to the parallel planes;

selectively applying electrical insulation over selected pads at which electrical connection is not desired by selectively depositing at least one of a spot or a line of dielectric material via a nozzle onto the selected region of the die, the selectively depositing leaving nonselected pads exposed and free from depositing of the dielectric material thereon, such that the nonselected interconnect pads are available for electrical interconnection without requiring the deposited dielectric material to be removed from the nonselected interconnect pads, the nozzle being controlled so that the dielectric material flows from the nozzle during intervals when a flow axis of the nozzle is directed at the selected interconnect pad and does not flow from the nozzle during intervals when the flow axis is directed at an unselected interconnect pad; and

forming electrically conductive traces over the columns, wherein at least one trace electrically interconnects the nonselected interconnect pads in a column of the plurality of columns.

15. The method of claim 14, wherein the plurality of said die are in an offset configuration in which successive die in the stack are offset at the interconnect die edge.

17. The method of claim 14, wherein forming the electrically conductive traces comprises depositing an electrically conductive material in flowable form and subsequently curing the material to form the trace.

18. The method of claim 14, wherein the selectively depositing the dielectric material comprises directing an aerosolized electrically insulative material onto the selected region.

19. The method of claim 14, wherein the selectively depositing the dielectric material includes directing a curable electrically insulative material onto the selected region, and then curing the material.

20. The method of claim 14, wherein the selected region of the die includes a selected region of a die sidewall, and the selectively depositing the dielectric material deposits the dielectric material onto the selected region of the die sidewall.