Semiconductor device

• US 9,490,267 B2
• Filed: 01/16/2015
• Issued: 11/08/2016
• Est. Priority Date: 01/28/2011
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Fujita, Masashi, Shionoiri, Yutaka, Tomatsu, Hiroyuki, Kobayashi, Hidetomo
• Primary Examiner(s): Ho, Hoai V
• Assistant Examiner(s): HOANG, TRI M
• Application Number:
  US14/598,384
• Publication Number:
  US 20150129873A1
• Time in Patent Office: 662 Days
• Field of Search: 257/43
• US Class Current: 1/1
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 27/1222 with a particular composition, shape or crystalline structure of the active layer
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/1251 comprising TFTs having a different architecture, e.g. top- and bottom gate TFTs
• CPC Class Codes: H10B 12/00 Dynamic random access memory [DRAM] devices
• CPC Class Codes: H10B 41/70 the floating gate being an electrode shared by two or more components

Abstract

A first field-effect transistor provided over a substrate in which an insulating region is provided over a first semiconductor region and a second semiconductor region is provided over the insulating region; an insulating layer provided over the substrate; a second field-effect transistor that is provided one flat surface of the insulating layer and includes an oxide semiconductor layer; and a control terminal are provided. The control terminal is formed in the same step as a source and a drain of the second field-effect transistor, and a voltage for controlling a threshold voltage of the first field-effect transistor is supplied to the control terminal.

Claims

1. A semiconductor device comprising:

a bus interface;

a control unit;

a cache memory which is controlled by the control unit and temporarily retains data during arithmetic processing;

N registers, wherein N is a natural number greater than or equal to 3;

an instruction decoder which translates an instruction signal read from at least one of the N registers and outputs the translated instruction signal to the control unit; and

an arithmetic logic unit which is controlled by the control unit and performs arithmetic processing,

wherein the N registers comprises a plurality of unit memory devices,

wherein the plurality of unit memory devices each comprise a first transistor and a second transistor,

wherein the first transistor comprises;

a first semiconductor layer comprising;

a first region having a first conductivity type;

a second region having the first conductivity type;

a third region in contact with the first region and the second region; and

a fourth region having a second conductivity type opposite to the first conductivity type and being in contact with the third region;

a first electrode over the third region of the first semiconductor layer with a first insulating layer provided therebetween;

a second electrode over the first insulating layer, wherein the second electrode is electrically connected to the first region of the first semiconductor layer;

a third electrode over the first insulating layer, wherein the third electrode is electrically connected to the second region of the first semiconductor layer; and

a fourth electrode over the first insulating layer and electrically connected to the fourth region, and

wherein the second transistor comprises a second semiconductor layer comprising oxide semiconductor.

2. The semiconductor device according to claim 1, wherein the oxide semiconductor comprises indium, gallium, and zinc.

3. The semiconductor device according to claim 1, wherein the fourth region of the first semiconductor layer overlaps with the second semiconductor layer.

4. The semiconductor device according to claim 1, further comprising a second insulating layer over the first insulating layer, wherein the second semiconductor layer is provided over the second insulating layer.

5. The semiconductor device according to claim 1, wherein the first semiconductor layer is provided over a silicon substrate.

6. The semiconductor device according to claim 1, wherein the first semiconductor layer comprises single crystal silicon.

7. An electronic device comprising a CPU comprising the semiconductor device according to claim 1, wherein the electronic device is one selected from the group consisting of a telephone set, an e-book reader, a personal computer, and a game machine.

8. A semiconductor device comprising:

a first memory circuit comprising;

a first transistor comprising;

a first gate;

a first source; and

a first drain;

a second transistor comprising;

a second gate electrically connected to one of the first source and the first drain;

a second source;

a second drain; and

a first terminal;

a first capacitor comprising;

a second terminal electrically connected to the one of the first source and the first drain and the second gate; and

a third terminal electrically connected to one of the second source and the second drain;

a third transistor comprising;

a third gate;

a third source; and

a third drain, wherein one of the third source and the third drain is electrically connected to the other of the second source and the second drain;

a fourth transistor comprising;

a fourth gate electrically connected to the third gate;

a fourth source; and

a fourth drain, wherein one of the fourth source and the fourth drain is electrically connected to the other of the third source and the third drain;

a second capacitor comprising;

a fourth terminal electrically connected to the other of the third source and the third drain and the one of the fourth source and the fourth drain; and

a fifth terminal electrically connected to the one of the second source and the second drain and the third terminal of the first capacitor;

a NOT gate comprising;

a first input terminal electrically connected to the other of the third source and the third drain, the one of the fourth source and the fourth drain, and the fourth terminal of the second capacitor; and

a first output terminal;

a switching circuit comprising;

a second input terminal electrically connected to the other of the first source and the first drain;

a third input terminal electrically connected to the first output terminal of the NOT gate; and

a second output terminal;

a second memory circuit comprising;

a fourth input terminal electrically connected to the second output terminal of the switching circuit; and

a third output terminal electrically connected to the second input terminal of the switching circuit and the other of the first source and the first drain,

wherein;

the second transistor comprises;

a first semiconductor layer comprising;

a first region having a first conductivity type;

a second region having the first conductivity type;

a third region in contact with the first region and the second region; and

a fourth region having a second conductivity type opposite to the first conductivity type and being in contact with the third region;

the second gate over the third region of the first semiconductor layer with a first insulating layer provided therebetween;

the second source over the first insulating layer, wherein the second source is electrically connected to the first region of the first semiconductor layer; and

the second drain over the first insulating layer, wherein the second drain is electrically connected to the second region of the first semiconductor layer;

the first transistor comprises;

a second semiconductor layer comprising oxide semiconductor, wherein the second semiconductor layer is provided over the first insulating layer;

the first source electrically connected to the second semiconductor layer;

the first drain electrically connected to the second semiconductor layer; and

the first gate over the second semiconductor layer with a second insulating layer provided therebetween, and

the first terminal is provided over the first insulating layer and electrically connected to the fourth region.

9. The semiconductor device according to claim 8, wherein the oxide semiconductor comprises indium, gallium, and zinc.

10. The semiconductor device according to claim 8, wherein the fourth region of the first semiconductor layer overlaps with the first gate.

11. The semiconductor device according to claim 8, further comprising a third insulating layer over the first insulating layer, wherein the second semiconductor layer, the first source, the first drain, the first gate are provided over the third insulating layer.

12. The semiconductor device according to claim 8, wherein the first semiconductor layer comprises single crystal silicon.

13. The semiconductor device according to claim 8, wherein the first source and the first drain are provided on the second semiconductor layer.

14. An electronic device comprising a CPU comprising the semiconductor device according to claim 8, wherein the electronic device is one selected from the group consisting of a telephone set, an e-book reader, a personal computer, and a game machine.

15. A semiconductor device comprising:

a first transistor comprising;

a first semiconductor layer comprising;

a first region having a first conductivity type;

a second region having the first conductivity type;

a third region in contact with the first region and the second region; and

a fourth region having a second conductivity type opposite to the first conductivity type and being in contact with the third region;

a first electrode over the third region of the first semiconductor layer with a first insulating layer provided therebetween;

a second electrode over the first insulating layer, wherein the second electrode is electrically connected to the first region of the first semiconductor layer;

a third electrode over the first insulating layer, wherein the third electrode is electrically connected to the second region of the first semiconductor layer; and

a fourth electrode over the first insulating layer and electrically connected to the fourth region;

a second transistor comprising a second semiconductor layer comprising oxide semiconductor, wherein the second semiconductor layer is provided over the first insulating layer.

16. The semiconductor device according to claim 15, wherein the oxide semiconductor comprises indium, gallium, and zinc.

17. The semiconductor device according to claim 15, wherein the fourth region of the first semiconductor layer overlaps with the second semiconductor layer.

18. The semiconductor device according to claim 15, wherein the first semiconductor layer is provided over a silicon substrate.

19. The semiconductor device according to claim 15, wherein the first semiconductor layer comprises single crystal silicon.

20. An electronic device comprising a CPU comprising the semiconductor device according to claim 15, wherein the electronic device is one selected from the group consisting of a telephone set, an e-book reader, a personal computer, and a game machine.