Extra gate device for nanosheet

• US 9,490,335 B1
• Filed: 12/30/2015
• Issued: 11/08/2016
• Est. Priority Date: 12/30/2015
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Doris, Bruce B., Hook, Terence B., Wang, Junli
• Primary Examiner(s): Miyoshi, Jesse Y
• Application Number:
  US14/984,280
• Time in Patent Office: 314 Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02603 Nanowires
• CPC Class Codes: H01L 21/3065 Plasma etching; Reactive-ion etching
• CPC Class Codes: H01L 21/823412 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823437 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 21/823456 gate conductors with different shapes, lengths or dimensions
• CPC Class Codes: H01L 21/823462 with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
• CPC Class Codes: H01L 21/8238 Complementary field-effect transistors, e.g. CMOS
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823828 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 21/82385 gate conductors with different shapes, lengths or dimensions
• CPC Class Codes: H01L 21/823857 with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
• CPC Class Codes: H01L 21/823892 with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
• CPC Class Codes: H01L 21/845 including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 27/0922 Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS
• CPC Class Codes: H01L 27/0928 comprising both N- and P- wells in the substrate, e.g. twin-tub
• CPC Class Codes: H01L 29/0665 the shape of the body defining a nanostructure nanotechnology per se B82B
• CPC Class Codes: H01L 29/0673 oriented parallel to a substrate
• CPC Class Codes: H01L 29/16 : including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
• CPC Class Codes: H01L 29/161 : including two or more of the elements provided for in group H01L29/16 , e.g. alloys H01L29/1604 takes precedence
• CPC Class Codes: H01L 29/165 : in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/42368 : the thickness being non-uniform
• CPC Class Codes: H01L 29/42392 : fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/66439 : with a one- or zero-dimensional channel, e.g. quantum wire FET, in-plane gate transistor [IPG], single electron transistor [SET], striped channel transistor, Coulomb blockade transistor with an active layer made of a group 13/15 material H01L29/66469
• CPC Class Codes: H01L 29/66545 : using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66772 : Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates H01L29/66666 takes precedence; thin film FinFETs H01L29/66795
• CPC Class Codes: H01L 29/775 : with one dimensional charge carrier gas channel, e.g. quantum wire FET
• CPC Class Codes: H01L 29/785 : having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/78654 : Monocrystalline silicon transistors
• CPC Class Codes: H01L 29/78696 : characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621
• CPC Class Codes: Y10S 977/938 : Field effect transistors, FETS, with nanowire- or nanotube-channel region

Abstract

A method for forming semiconductor devices includes forming a highly doped region. A stack of alternating layers is formed on the substrate. The stack is patterned to form nanosheet structures. A dummy gate structure is formed over and between the nanosheet structures. An interlevel dielectric layer is formed. The dummy gate structures are removed. SG regions are blocked, and top sheets are removed from the nanosheet structures along the dummy gate trench. A bottommost sheet is released and forms a channel for a field effect transistor device by etching away the highly doped region under the nanosheet structure and layers in contact with the bottommost sheet. A gate structure is formed in and over the dummy gate trench wherein the bottommost sheet forms a device channel for the EG device.

Claims

1. A method for forming semiconductor devices, comprising:

doping a surface of a substrate in exposed areas where extra gate (EG) devices are to be formed to form a highly doped region;

forming a stack of alternating layers on the substrate over single gate (SG) regions and the EG regions;

patterning the stack to form nanosheet structures;

forming a dummy gate structure over and between the nanosheet structures;

forming an interlevel dielectric layer over the dummy gate structure and the nanosheet structures;

removing dummy gate structures to form a dummy gate trench;

blocking the SG regions;

removing top sheets from the nanosheet structures along the dummy gate trench;

releasing at least one bottommost sheet including a semiconductor layer to form a channel for a field effect transistor device by etching away the highly doped region under the nanosheet structure and layers in contact with the at least one bottom most sheet; and

forming a gate structure in and over the dummy gate trench wherein the at least one bottommost sheet forms a device channel for the EG device.

2. The method as recited in claim 1, wherein forming the gate structure includes:

depositing a first dielectric layer;

blocking one of the SG regions and the EG regions; and

adjusting a thickness of the first dielectric layer of the other of the SG regions and the EG regions that is unblocked.

3. The method as recited in claim 1, wherein the nanosheet structures are formed over N wells and P wells to form P-type and N-type devices for SG devices and EG devices.

4. The method as recited in claim 1, wherein the nano sheet structures are formed by epitaxially growing alternating layers of the Si and SiGe.

5. The method as recited in claim 1, wherein the SG devices include thinner gate dielectric than EG devices.

6. The method as recited in claim 1, wherein forming the gate structure includes forming an oxide on the at least one bottommost sheet and depositing a gate dielectric layer on the oxide.

7. The method as recited in claim 6, further comprising forming a gate conductor in the gate structure.

8. The method as recited in claim 1, wherein the stack of alternating layers includes at least three semiconductor layers and the at least one bottommost layer includes a third semiconductor layer.