Method for fabricating semiconductor device

• US 9,490,342 B2
• Filed: 06/16/2011
• Issued: 11/08/2016
• Est. Priority Date: 06/16/2011
• Status: Active Grant

• Current Assignee: United Microelectronics Corporation
• Original Assignee: United Microelectronics Corporation
• Inventors: Lin, Kun-Hsien, Lai, Chien-Ming, Chen, Yi-Wen, Lee, Zhi-Cheng, Huang, Tong-Jyun, Hsu, Che-Hua, Lee, Tzung-Ying, Hsu, Chi-Mao, Huang, Hsin-Fu, Lin, Chin-Fu
• Primary Examiner(s): Dang, Trung Q
• Application Number:
  US13/161,591
• Publication Number:
  US 20120322218A1
• Time in Patent Office: 1,972 Days
• Field of Search: 438/585, 438/303, 257/E21.444
• US Class Current: 1/1
• CPC Class Codes: H01L 21/28088 the final conductor layer next to the insulator being a composite, e.g. TiN
• CPC Class Codes: H01L 21/32134 by liquid etching only
• CPC Class Codes: H01L 21/823842 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/4966 the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/518 the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618

Abstract

A method for fabricating a semiconductor device includes the following steps. Firstly, a dummy gate structure having a dummy gate electrode layer is provided. Then, the dummy gate electrode layer is removed to form an opening in the dummy gate structure, thereby exposing an underlying layer beneath the dummy gate electrode layer. Then, an ammonium hydroxide treatment process is performed to treat the dummy gate structure. Afterwards, a metal material is filled into the opening.

Claims

1. A method for fabricating a semiconductor device, the method comprising steps of:

providing a dummy gate structure having a dummy gate electrode layer;

removing the dummy gate electrode layer to form an opening in the dummy gate structure, thereby exposing an underlying layer beneath the dummy gate electrode layer;

performing an ammonium hydroxide treatment process to treat the dummy gate structure; and

filling a metal material into the opening, wherein the ammonium hydroxide treatment process is performed in an ammonium hydroxide solution at an operating temperature of 60°

C., wherein the ammonium hydroxide solution is a mixture of ammonium hydroxide and water in a ratio of 1;

120, wherein

at least one-third of the dummy gate electrode layer is removed by a pre-etching process, and at least one half of the dummy gate electrode layer is removed by the ammonium hydroxide treatment process.

2. The method according to claim 1, wherein the dummy gate structure comprises:

a gate oxide layer formed on a substrate;

a barrier layer formed on the gate oxide layer;

the dummy gate electrode layer formed on the barrier layer; and

a spacer formed over the substrate to surround the gate oxide layer, the barrier layer and the dummy gate electrode layer.

3. The method according to claim 2, wherein the step of removing the dummy gate electrode layer further comprises a step of pulling back the spacer.

4. The method according to claim 2, wherein the gate oxide layer is made of a high dielectric constant material, wherein after the gate oxide layer is formed, an ion-implanting process is performed to form source/drain regions in the substrate and adjacent to the dummy gate structure.

5. The method according to claim 1, further comprising steps of:

performing an ion-implanting process to form source/drain regions in the substrate and adjacent to the dummy gate structure before the step of removing the dummy gate electrode layer is performed; and

forming a high-k dielectric layer within the opening after the ammonium hydroxide treatment process is performed.

6. The method according to claim 1, wherein the step of removing the dummy gate electrode layer and the ammonium hydroxide treatment process are performed in the same process vessel.

7. A method for fabricating a semiconductor device, the method comprising steps of:

providing a dummy gate structure having a dummy gate electrode layer;

performing a pre-etching process to remove a portion of the dummy gate electrode layer;

performing an ammonium hydroxide treatment process to remove the remaining dummy gate electrode layer, thereby forming an opening in the dummy gate structure and exposing an underlying layer beneath the dummy gate electrode layer; and

filling a metal material into the opening, wherein the ammonium hydroxide treatment process is performed in an ammonium hydroxide solution at an operating temperature of 60°

C., wherein the ammonium hydroxide solution is a mixture of ammonium hydroxide and water in a ratio of 1;

120 wherein

at least one-third of the dummy gate electrode layer is removed by the pre-etching process, and at least one half of the dummy gate electrode layer is removed by the ammonium hydroxide treatment process.

8. The method according to claim 7, wherein the pre-etching process is a wet etching process carried out in a tetramethylammonium hydroxide (TMAH) solution.

9. The method according to claim 7, wherein the dummy gate structure comprises:

a gate oxide layer formed on a substrate;

a barrier layer formed on the gate oxide layer;

the dummy gate electrode layer formed on the barrier layer; and

a spacer formed over the substrate to surround the gate oxide layer, the barrier layer and the dummy gate electrode layer.

10. The method according to claim 9, further comprising a step of pulling back the spacer after the pre-etching process and before the ammonium hydroxide treatment process.

11. The method according to claim 9, wherein the gate oxide layer is made of a high dielectric constant material, wherein after the gate oxide layer is formed, an ion-implanting process is performed to form source/drain regions in the substrate and adjacent to the dummy gate structure.

12. The method according to claim 7, further comprising steps of:

performing an ion-implanting process to form source/drain regions in the substrate and adjacent to the dummy gate structure before the step of removing the dummy gate electrode layer is performed; and

forming a high-k dielectric layer within the opening after the ammonium hydroxidetreatment process is performed.

13. The method according to claim 7, wherein the step of removing the portion of the dummy gate electrode layer and the ammonium hydroxide treatment process are performed in the same process vessel.