Charge pump with switching gate bias

• US 9,490,696 B2
• Filed: 02/09/2015
• Issued: 11/08/2016
• Est. Priority Date: 02/09/2015
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Park, Dongmin, Leung, Lai Kan, Park, Jong Min
• Primary Examiner(s): POOS, JOHN W
• Application Number:
  US14/617,025
• Publication Number:
  US 20160233763A1
• Time in Patent Office: 638 Days
• Field of Search: 327/147, 327/148, 327/149, 327/156, 327/158, 327/161, 327/534, 327/536
• US Class Current: 1/1
• CPC Class Codes: H02M 3/07 using capacitors charged and discharged alternately by semiconductor devices with control electrode , e.g. charge pumps
• CPC Class Codes: H03L 7/0895 Details of the current generators H03L7/0893 takes precedence
• CPC Class Codes: H03L 7/093 using special filtering or amplification characteristics in the loop H03L7/087 - H03L7/091 take precedence
• CPC Class Codes: H03L 7/099 concerning mainly the controlled oscillator of the loop

Abstract

An apparatus including: a current source configured to generate current; a bias node coupled to the current source; a switching current source circuit coupled to the current source and the bias node to allow the current to flow through the switching current source circuit into the bias node; a biasing circuit configured to receive a control signal from a phase detector, and mirror the current flowing through the switching current source circuit in response to the control signal; and a switch device disposed between the switching current source circuit and the biasing circuit to isolate the switching current source circuit from the biasing circuit.

Claims

1. An apparatus comprising:

a current source configured to generate current;

a bias node coupled to the current source;

a switching current source circuit coupled to the current source and the bias node to allow the current to flow through the switching current source circuit into the bias node;

a biasing circuit configured to receive a control signal from a phase detector, and mirror the current flowing through the switching current source circuit in response to the control signal,

wherein the biasing circuit comprises a second transistor having gate, source, and drain terminals, a third transistor having gate, source, and drain terminals, and a second capacitor,

wherein the gate terminal of the third transistor receives the control signal, the drain terminal of the third transistor is coupled to the source terminal of the second transistor, and the source terminal of the third transistor is coupled to a ground voltage;

a switch device disposed between the switching current source circuit and the biasing circuit to isolate the switching current source circuit from the biasing circuit,

wherein the gate terminal of the second transistor is coupled to the switch device; and

an output node coupled to the drain terminal of the second transistor.

2. The apparatus of claim 1, wherein the apparatus is a charge pump of a phase-locked loop.

3. The apparatus of claim 1, wherein the switch device is configured to receive the control signal.

4. The apparatus of claim 3, wherein the control signal activates the switch device.

5. The apparatus of claim 1, wherein the switch device comprises a first terminal, a second terminal, and a pair of fourth and fifth transistors.

6. The apparatus of claim 5, wherein drain and source terminals of the fourth and fifth transistors, respectively, are coupled to the first terminal and drain and source terminals of the fifth and fourth transistors, respectively, are coupled to the second terminal.

7. The apparatus of claim 6, wherein a gate terminal of the fifth transistor is configured to receive the control signal and a gate terminal of the fourth transistor is configured to receive a complementary control signal.

8. The apparatus of claim 1, wherein the switching current source circuit comprises a first transistor configured with a gate terminal coupled to the bias node, a drain terminal coupled to the current source and the gate terminal, and a source terminal coupled to the ground voltage.

9. The apparatus of claim 8, further comprising a first capacitor coupled to the gate terminal of the first transistor and the ground voltage.

10. The apparatus of claim 9, wherein the switch device comprises first and second terminals, the first terminal coupled to the gate terminal of the first transistor.

11. A charge pump, comprising:

a biasing circuit configured to receive a control signal from a phase detector and output a current pulse train signal to an output node,

wherein the biasing circuit comprises a third transistor having gate, source, and drain terminals, a fourth transistor having gate, source, and drain terminals, and a first capacitor,

wherein the gate terminal of the fourth transistor receives the control signal, the drain terminal of the fourth transistor is coupled to the source terminal of the third transistor, the source terminal of the fourth transistor is coupled to a ground voltage, and the drain terminal of the third transistor is coupled to the output node;

a switching current source circuit configured to enable current to flow through and into a bias node and to mirror the current onto the biasing circuit; and

a switch device disposed between the biasing circuit and the switching current source circuit,

wherein the switch device isolates the biasing circuit and the switching current source circuit so that the bias node and the biasing circuit are not affected by switching activities of the switching current source circuit,

wherein the gate terminal of the third transistor is coupled to the switch device.

12. The charge pump of claim 11, wherein the switch device comprises

first and second transistors, the first transistor configured as a p-type metal oxide semiconductor field-effect transistor (MOSFET) and the second transistor configured as an n-type MOSFET.

13. The charge pump of claim 12, wherein the n-type MOSFET is configured with a gate terminal to receive the control signal while the p-type MOSFET is configured with a gate terminal to receive a complementary control signal.

14. The charge pump of claim 11, wherein the switch device couples to the bias node.

15. A phase-locked loop, comprising:

a phase detector configured to receive a reference signal and a divider output signal and output a control signal and a complementary control signal;

a charge pump comprising;

a biasing circuit configured to receive the control signal from the phase detector and output a current pulse train signal to an output node,

wherein the biasing circuit comprises a third transistor having gate, source, and drain terminals, a fourth transistor having gate, source, and drain terminals, and a first capacitor,

wherein the gate terminal of the fourth transistor receives the control signal, the drain terminal of the fourth transistor is coupled to the source terminal of the third transistor, the source terminal of the fourth transistor is coupled to a ground voltage, and the drain terminal of the third transistor is coupled to the output node;

a switching current source circuit configured to enable current to flow through and into a bias node and to mirror the current onto the biasing circuit; and

a switch device disposed between the biasing circuit and the switching current source circuit,

wherein the switch device isolates the biasing circuit and the switching current source circuit so that the bias node and the biasing circuit are not affected by switching activities of the switching current source circuit,

wherein the gate terminal of the third transistor is coupled to the switch device;

a low pass filter configured to receive the current pulse train signal and output a control voltage;

a voltage controlled oscillator configured to receive the control voltage and output a corresponding frequency signal; and

a frequency divider configured receive the corresponding frequency signal and output the divider output signal for feedback to the phase detector.

16. The phase-locked loop of claim 15, wherein the switch device comprises

first and second transistors, the first transistor configured as a p-type metal oxide semiconductor field-effect transistor (MOSFET) and the second transistor configured as an n-type MOSFET.

17. The phase-locked loop of claim 16, wherein the n-type MOSFET is configured with a gate terminal to receive the control signal while the p-type MOSFET is configured with a gate terminal to receive the complementary control signal.