Analog-to-digital converter circuit and method of implementing an analog-to-digital converter circuit

• US 9,490,832 B1
• Filed: 11/16/2015
• Issued: 11/08/2016
• Est. Priority Date: 11/16/2015
• Status: Active Grant

• Current Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Original Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Inventors: Zhou, Lei, Hedayati, Hiva
• Primary Examiner(s): Pierre, Peguy Jean
• Application Number:
  US14/942,601
• Time in Patent Office: 358 Days
• Field of Search: 341/144, 341/155, 341/172, 341/163, 341/143
• US Class Current: 1/1
• CPC Class Codes: H03K 3/35613 the input circuit having a differential configuration
• CPC Class Codes: H03M 1/0872 by disabling changes in the output during the transitions, e.g. by holding or latching
• CPC Class Codes: H03M 1/468 in which the input S/H circuit is merged with the feedback DAC array

Abstract

An analog-to-digital converter circuit is described. The analog-to-digital converter circuit comprises an amplifier circuit configured to receive a differential analog input signal at a first amplifier input associated with a first amplifier current path and a second amplifier input associated with a second amplifier current path, and to generate an amplified differential analog input signal at a first amplifier output associated with the first amplifier current path and a second amplifier output associated with the second amplifier current path; a first capacitor coupled between the first amplifier input and the second amplifier output; a second capacitor coupled between the second amplifier input and the first amplifier output; and a latch circuit having a first latch input coupled to the first amplifier output and a second latch input coupled to the second amplifier output, wherein the latch circuit is configured to generate a differential digital output signal, based upon the amplified differential analog input signal, at a first latch output and a second latch output.

Claims

1. An analog-to-digital converter circuit comprising:

an amplifier circuit configured to receive a differential analog input signal at a first amplifier input associated with a first amplifier current path and a second amplifier input associated with a second amplifier current path, and to amplify the differential analog input signal to generate a differential analog output signal at a first amplifier output associated with the first amplifier current path and at a second amplifier output associated with the second amplifier current path, wherein;

the amplifier circuit comprises a first resistive load coupled between a reference voltage and a first transistor of the first amplifier current path;

a first input signal of the differential analog input signal is coupled to a gate of the first transistor;

the amplifier circuit further comprises a second resistive load coupled between the reference voltage and a second transistor of the second amplifier current path; and

a second input signal of the differential analog input signal is coupled to a gate of the second transistor;

a first capacitor coupled between the first amplifier input and the second amplifier output;

a second capacitor coupled between the second amplifier input and the first amplifier output; and

a latch circuit having a first latch input coupled to the first amplifier output and a second latch input coupled to the second amplifier output, wherein the latch circuit is configured to generate a differential digital output signal, based upon the differential analog output signal, at a first latch output and a second latch output.

2. The analog-to-digital converter circuit of claim 1 wherein the first capacitor and the second capacitor are approximately 2 femtofarads.

3. The analog-to-digital converter circuit of claim 1 wherein:

the first capacitor comprises a third transistor having a source connected to a drain to form a source/drain node of the third transistor;

one of a gate and the source/drain node of the third transistor is coupled to a gate of the first transistor; and

the other of the gate and the source/drain node of the third transistor is coupled to a drain of the second transistor.

4. The analog-to-digital converter circuit of claim 3 wherein:

the second capacitor comprises a fourth transistor having a source connected to a drain to form a source/drain node of the fourth transistor;

one of a gate and the source/drain node of the fourth transistor is coupled to a gate of the second transistor; and

the other of the gate and the source/drain node of the fourth transistor is coupled to a drain of the first transistor.

5. The analog-to-digital converter circuit of claim 4 wherein the third transistor and the fourth transistor have gate widths that are approximately one half the gate widths of the first transistor and the second transistor.

6. The analog-to-digital converter circuit of claim 1 further comprising a capacitive digital-to-analog converter circuit having a first plurality of capacitors that are coupled to the first amplifier input of the amplifier circuit to provide a first analog voltage to the first amplifier input.

7. The analog-to-digital converter circuit of claim 6 wherein the capacitive digital-to-analog converter circuit further comprises a second plurality of capacitors that are coupled to the second amplifier input of the amplifier circuit to provide a second analog voltage to the second amplifier input.

8. The analog-to-digital converter circuit of claim 1 further comprising a successive approximation register circuit having a first input coupled to the first latch output and a second input coupled to the second latch output.

9. The analog-to-digital converter circuit of claim 8 wherein the successive approximation register circuit generates an output value indicating a voltage level of the differential input signal.

10. A method of implementing an analog-to-digital converter circuit comprising:

receiving a differential analog input signal at a first amplifier input of a first amplifier path of an amplifier circuit and a second amplifier input of a second amplifier path of the amplifier circuit;

reducing noise at the first amplifier input and the second amplifier input via a first capacitor coupled between the first amplifier input and a second amplifier output associated with the second amplifier path and via a second capacitor coupled between the second amplifier input and a first amplifier output associated with a first amplifier path;

amplifying the differential analog input signal to generate a differential analog output signal at the first amplifier output and the second amplifier output;

latching data at a first latch input that is coupled to the first amplifier output and at a second latch input that is coupled to the second amplifier output; and

generating a differential digital output signal, based upon the differential analog output signal, at a first latch output and a second latch output;

wherein;

a first resistive load is coupled between a reference voltage and a first transistor of the first amplifier current path;

a first input signal of the differential analog input signal is coupled to a gate of the first transistor;

a second resistive load is coupled between the reference voltage and a second transistor of the second amplifier current path; and

a second input signal of the differential analog input signal is coupled to a gate of the second transistor.

11. The method of claim 10 wherein the first capacitor and the second capacitor are approximately 2 femtofarads.

12. The method of claim 10 wherein:

the first capacitor comprises a third transistor having a source connected to a drain to form a source/drain node of the third transistor;

one of a gate and the source/drain node of the third transistor is coupled to the gate of the first transistor; and

the other of the gate and the source/drain node of the third transistor is coupled to a drain of the second transistor.

13. The method of claim 12 wherein:

the second capacitor comprises a fourth transistor having a source connected to a drain to form a source/drain node of the fourth transistor;

one of a gate and the source/drain node of the fourth transistor is coupled to the gate of the second transistors; and

the other of the gate and the source/drain node of the fourth transistor is coupled to a drain of the first transistor.

14. The method of claim 13 wherein the third transistor and the fourth transistor have gate widths that are approximately one half the gate widths of the first and second transistors.

15. The method of claim 10 further comprising coupling a first plurality of capacitors to the first amplifier input of the amplifier circuit to provide a first analog voltage to the first amplifier input.

16. The method of claim 15 further comprising coupling a second plurality of capacitors to the second amplifier input of the amplifier circuit to provide a second analog voltage to the second amplifier input.

17. The method of claim 10 further comprising coupling a first input of a successive approximation register circuit to the first latch output and a second input of the successive approximation register to the second latch output.

18. The method of claim 17 further comprising generating an output value indicating a voltage level of the differential analog input signal at an output of the successive approximation register circuit.