Coordinated signal reception across integrated circuit boundaries

• US 9,490,864 B2
• Filed: 05/12/2014
• Issued: 11/08/2016
• Est. Priority Date: 01/14/2011
• Status: Active Grant

• Current Assignee: Apple Inc.
• Original Assignee: Apple Inc.
• Inventors: Mujtaba, Syed A., Chaudhary, Madhusudan, Elangovan, Thanigaivelu, Anantharaman, Karthik, Dou, Weiping, Mahe, Isabel G.
• Primary Examiner(s): Abelson, Ronald B
• Application Number:
  US14/275,286
• Publication Number:
  US 20140242925A1
• Time in Patent Office: 911 Days
• Field of Search: 370/311, 370/328
• US Class Current: 1/1
• CPC Class Codes: H04B 1/44 Transmit/receive switching
• CPC Class Codes: H04B 7/0608 Antenna selection according to transmission parameters
• CPC Class Codes: H04B 7/0689 using different transmission schemes, at least one of them being a diversity transmission scheme
• CPC Class Codes: H04B 7/0802 using antenna selection H04B7/0868 takes precedence; antenna beam directivity switching H01Q3/24
• CPC Class Codes: H04W 52/02 Power saving arrangements in wired systems H04L12/12; signaling of mobile application services, e.g. low battery notifications H04W4/20
• CPC Class Codes: H04W 52/028 switching on or off only a part of the equipment circuit blocks
• CPC Class Codes: Y02D 30/70 in wireless communication networks

Abstract

A wireless electronic device having first and second baseband processors is provided. In one suitable arrangement, radio-frequency power splitters and adjustable low noise amplifiers may be form in the receive paths. The use of power splitters allow signals associated with the first and second baseband processors to be received in parallel. In another suitable arrangement, radio-frequency switches are used in place of the power splitters. The states of the switches may be controlled using at least one of the first and second baseband processors. The use of switches instead of power splitters requires that wake periods associated with the first baseband processor and wake periods associated with the second baseband processor are non-overlapping. To ensure minimal wake period collision, a wake period associated with the second baseband processor may be positioned at a midpoint between two successive wake periods associated with the first baseband processor.

Claims

1. A wireless electronic device, comprising:

an antenna;

a transceiver circuit coupled to the antenna;

a radio-frequency diplexer coupled to the antenna; and

a first baseband processor coupled to the transceiver circuit, wherein the first baseband processor operates in a sleep state from which the first baseband processor awakens for a first wake period, and the first baseband processor is configured to;

monitor for a first paging signal associated with the first baseband processor during the first wake period; and

in response to the first paging signal being absent during the first wake period, generate control signals to cause a second baseband processor coupled to the antenna in the wireless electronic device to avoid collisions between the first wake period of the first baseband processor and a second wake period of the second baseband processor, wherein the control signals are generated based at least in part on a predetermined amount of time that expires at an approximate midpoint between successive slots of a first cycle associated with the first wake period.

2. The wireless electronic device defined in claim 1, further comprising:

an application processor coupled to the first baseband processor.

3. The wireless electronic device defined in claim 1, further comprising:

a radio-frequency duplexer coupled between the radio-frequency diplexer and the transceiver circuit.

4. The wireless electronic device defined in claim 1, further comprising:

a first radio-frequency switch that switchably couples the transceiver circuit to the radio-frequency diplexer, wherein the first radio-frequency switch is configured to pass uplink radio-frequency signals; and

a second radio-frequency switch that switchably couples the radio-frequency diplexer to the transceiver circuit, wherein the second radio-frequency switch is configured to pass downlink radio-frequency signals,

wherein the first radio-frequency switch and the second radio-frequency switch are controlled by the first baseband processor.

5. The wireless electronic device defined in claim 1, wherein the first baseband processor supports cellular radio access technologies.

6. The wireless electronic device defined in claim 1, wherein the first baseband processor supports a long term evolution (LTE) protocol or a Bluetooth protocol.

7. The wireless electronic device defined in claim 1, wherein the first baseband processor awakens during a slot of the first cycle associated with the first wake period, and the slot during which the first baseband processor awakens is based at least in part on an identifier that is unique to the wireless electronic device.

8. The wireless electronic device defined in claim 1, wherein the second baseband processor awakens for the second wake period based at least in part on the control signals.

9. The wireless electronic device defined in claim 1, wherein the first baseband processor is further configured to:

in response to detecting the first paging signal during the first wake period, generate control signals to cause the first baseband processor to be placed in an active traffic mode.

10. A method for operating an electronic device including a first baseband processor integrated circuit, a first antenna, a transceiver coupled between the first baseband processor integrated circuit and the first antenna, and a radio-frequency diplexer coupled between the first antenna and the transceiver circuit, the method comprising:

monitoring, at the first baseband processor integrated circuit, for a first paging signal during a first wake period;

in response to the first paging signal being absent during the first wake period, sending information from the first baseband processor integrated circuit to a second baseband processor integrated circuit, the information configured to enable the second baseband processor integrated circuit in the electronic device to avoid collisions between the first wake period for the first baseband processor integrated circuit and a second wake period for the second baseband processor integrated circuit, and the information based at least in part on a predetermined amount of time that expires at an approximate midpoint between successive slots of a first cycle associated with the first wake period; and

communicating, via the transceiver and the radio-frequency diplexer, signals from the first baseband processor integrated circuit to the first antenna.

11. The method defined in claim 10,

wherein the first baseband processor integrated circuit awakens from a sleep state associated with the first baseband processor integrated circuit during the first wake period,

the second baseband processor integrated circuit awakens from a sleep state associated with the second baseband processor integrated circuit during the second wake period, and

the sending the information comprises sending a control signal from the first baseband processor integrated circuit to the second baseband processor integrated circuit, the control signal configured to cause the second baseband processor integrated circuit to configure the second baseband processor integrated circuit so that the first wake period and the second wake period are non-overlapping in time.

12. The method defined in claim 11, wherein the first wake period and second wake period are separated by the predetermined amount of time.

13. The method defined in claim 12, further comprising:

in response to detecting the first paging signal during the first wake period, placing the first baseband processor integrated circuit in a first baseband processor active traffic mode.

14. The method defined in claim 13, wherein the electronic device includes a second antenna, the method further comprising:

when the first wake period exceeds the predetermined amount of time, using the first antenna to handle the first baseband processor active traffic mode and using the second antenna to handle a second baseband processor active traffic mode for the second baseband processor integrated circuit.

15. The method defined in claim 13, further comprising:

when the first wake period exceeds the predetermined amount of time, preventing the second baseband processor integrated circuit from awakening from the second baseband processor integrated circuit'"'"'s sleep state.

16. The method defined in claim 13, wherein the first baseband processor integrated circuit comprises a cellular baseband processor integrated circuit, and placing the first baseband processor integrated circuit in the first baseband processor active traffic mode comprises establishing a live voice call.

17. An electronic device, comprising:

an antenna;

a first baseband processor;

a second baseband processor;

a transceiver circuit coupled between the first baseband processor and the antenna; and

a radio-frequency diplexer coupled between the antenna and the transceiver circuit, wherein the first baseband processor configured to;

monitor for a first paging signal associated with the first baseband processor during a first wake period; and

in response to the first paging signal being absent during the first wake period, send, to the second baseband processor, one or more signals that cause the second baseband processor to avoid collisions between the first wake period for the first baseband processor and a second wake period for the second baseband processor, wherein the one or more signals are generated based at least in part on a predetermined amount of time that expires at an a approximate midpoint between successive slots of a first cycle associated with the first wake period.

18. The electronic device defined in claim 17, further comprising an application processor.

19. The electronic device defined in claim 17, further comprising a radio-frequency duplexer coupled between the radio-frequency diplexer and the transceiver circuit.

20. The electronic device defined in claim 17, further comprising:

a first radio-frequency switch that switchably couples the transceiver circuit to the radio-frequency diplexer, wherein the first radio-frequency switch is configured to pass uplink radio-frequency signals; and

a second radio-frequency switch that switchably couples the radio-frequency diplexer to the transceiver circuit, wherein the second radio-frequency switch is configured to pass downlink radio-frequency signals,

wherein the first radio-frequency switch and the second radio-frequency switch are controlled by the first baseband processor.