Hardware-based time alignment of wireless links

• US 9,490,880 B1
• Filed: 01/07/2016
• Issued: 11/08/2016
• Est. Priority Date: 01/07/2016
• Status: Active Grant

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Srinivas, Raghavendra, Goel, Apoorv, Kaushik, Arvind, Prakash, Sachin
• Primary Examiner(s): Lam, Kenneth
• Application Number:
  US14/989,805
• Time in Patent Office: 306 Days
• US Class Current: 1/1
• CPC Class Codes: G06F 5/06 for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor G06F7/78 takes precedence
• CPC Class Codes: H04J 3/0685 Clock or time synchronisation in a node; Intranode synchronisation

Abstract

For a baseband digital front-end (BDFE) processor that communicates with one or more radio-frequency integrated circuit (RFIC) chips over two or more JESD-compliant links in a multi-antenna base station, the BDFE has JESD transmitters (TXs) and receivers (RXs) that transmit and receive data to and from the RFIC chips and a time-based generator (TBGEN) that generates sync and idle signals that ensure that the processing of the different JESD TXs and RXs are aligned in time for data associated with a single logical group of antennas. The TBGEN has hardware-based alignment circuitry that generates the sync and idle signals, thereby avoiding the latency and unpredictability inherent with software-based solutions.

Claims

1. An article of manufacture comprising a baseband digital front-end (BDFE) processor for a multiple-in, multiple-out (MIMO) system having one or more radio-frequency integrated circuit (RFIC) chips connected to the BDFE processor by way of multiple JESD204B lanes, the BDFE processor comprising:

one or more sync-alignment circuits comprising one or more sets of integrated circuits that generate multiple, time-aligned JESD204B SYNC˜

signals for a group of the JESD204B lanes based on a sync-to-lane mapping and a lane-to-group mapping; and

multiple idle generation circuits comprising multiple sets of the integrated circuits that generate multiple, time-aligned JESD204B IDLE signals for the group of the JESD204B lanes based on a group-to-idle mapping.

2. The article of claim 1, wherein the article is the MIMO system.

3. The article of claim 1, wherein:

the MIMO system comprises a plurality of RFIC chips, each RFIC chip corresponding to a plurality of the JESD204B lanes;

the BDFE processor comprises a plurality of the sync-alignment circuits and a different idle generation circuit for each different JESD204B lane;

the plurality of lanes are programmably assignable to one or more logical groups, each logical group comprising one or more of the lanes; and

each sync-alignment circuit is programmably assignable to a logical sub-group of one or more of the lanes assigned to one of the logical groups.

4. The article of claim 1, wherein, if two or more sync-alignment circuits are assigned to two or more sub-groupings of the same logical group, then the two or more sync-alignment circuits align their JESD204B SYNC˜

signals in time based on the same data pulse signal.

5. The article of claim 1, wherein the BDFE processor further comprises an edge detector that receives a data pulse signal and generates an edge signal indicating detection of a pulse in the data pulse signal, and wherein each sync-alignment circuit comprises:

a (2×

1) multiplexer (MUX) that receives first and second MUX input signals and a MUX control signal and presents one of the first and second MUX input signals as a MUX output signal based on the MUX control signal;

an AND gate that receives first and second AND input signals and generates an AND output signal; and

a flip-flop that receives a D input signal and a clock signal and presents the D input signal as a Q output signal based on the clock signal, wherein;

the MUX receives the Q output signal as the first MUX input signal, the first sync signal as the second MUX input signal, and the edge signal as the MUX control signal;

the AND gate receives the MUX output signal and the first sync signal as the first and second AND input signals;

the flip-flop receives the AND output signal as the D input signal; and

the Q output signal is the first aligned sync signal.

6. The article of claim 1, wherein the BDFE processor further comprises an edge detector that receives a data pulse signal and generates an edge signal indicating detection of a pulse in the data pulse signal, and wherein each idle-alignment circuit comprises:

a first (2×

1) MUX that receives first and second first-MUX input signals and a first-MUX control signal and presents one of the first and second first-MUX input signals as a first-MUX output signal based on the first-MUX control signal;

a second (2×

1) MUX that receives first and second second-MUX input signals and a second-MUX control signal and presents one of the first and second second-MUX input signals as a second-MUX output signal based on the second-MUX control signal;

a first OR gate that receives first and second first-OR input signals and generates a first-OR output signal;

a second OR gate that receives first and second second-OR input signals and generates a second-OR output signal; and

a flip-flop that receives a D input signal and a clock signal (REF_CLK) and presents the D input signal as a Q output signal based on the clock signal, wherein;

the first OR gate receives a group initial lane alignment (ILA) signal as the first first-OR input signal and the edge signal as the second first-OR input signal;

the first MUX receives the Q output signal as the first MUX input signal, the group ILA signal as the second MUX input signal, and the first-OR output signal as the first-MUX control signal;

the flip-flop receives the first-MUX output signal as the D input signal;

the second OR gate receives a delayed version of the data pulse signal as the first second-OR input signal and the Q output signal as the second second-OR input signal;

the second MUX receives the delayed version of the data pulse signal as the first second-MUX input signal, the second-OR output signal as the second second-MUX input signal, and a group-to-idle look-up table (LUT) entry as the second-MUX control signal; and

the second-MUX output signal is the first aligned idle signal.