Phase synchronization of modulation or demodulation for QAM-based multiband TSV-link

• US 9,491,028 B2
• Filed: 11/23/2015
• Issued: 11/08/2016
• Est. Priority Date: 05/24/2013
• Status: Active Grant

• Current Assignee: Regents of the University of California (University of California)
• Original Assignee: Regents of the University of California (University of California)
• Inventors: Lee, Sheau Jiung, Li, Yilei, Cho, Wei-Han, Chang, Mau-Chung Frank
• Primary Examiner(s): Bayard, Emmanuel
• Application Number:
  US14/949,165
• Publication Number:
  US 20160149746A1
• Time in Patent Office: 351 Days
• Field of Search: 375219-222, 375354-358
• US Class Current: 1/1
• CPC Class Codes: H04L 2027/0022 using the carrier of the associated receiver of a transceiver
• CPC Class Codes: H04L 2027/0028 at passband only
• CPC Class Codes: H04L 2027/0055 single phase
• CPC Class Codes: H04L 2027/0067 Phase error detectors
• CPC Class Codes: H04L 27/3455 in order to facilitate carrier recovery at the receiver end, e.g. by transmitting a pilot or by using additional signal points to allow the detection of rotations
• CPC Class Codes: H04L 27/362 Modulation using more than one carrier, e.g. with quadrature carriers, separately amplitude modulated H04L27/366 takes precedence
• CPC Class Codes: H04L 27/364 Arrangements for overcoming imperfections in the modulator, e.g. quadrature error or unbalanced I and Q levels
• CPC Class Codes: H04L 27/3872 Compensation for phase rotation in the demodulated signal
• CPC Class Codes: H04L 7/0331 with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock H04L7/0337 takes precedence

Abstract

A chip-to-chip communications circuit which is particularly well-suited for short range wired RF communication from one integrated circuit (chip) to another is presented. The circuits preferably utilize multi-frequency quadrature amplitude modulation (QAM) mechanisms for converting digital data bits from a parallel form into a serial analog stream for communication over a chip I/O connection. During a phase calibration cycle, a phase adjustment controller in the transmitter interoperates with a phase adjustment controller in the receiver, to adjust a phase locked-loop (PLL) circuit to correct for the phase delay arising in response to signal propagation between transmitter and receiver.

Claims

1. An apparatus for obtaining phase synchronization between modulation at a transmitter and demodulation at a receiver, comprising:

(a) a modulation circuit within a transmitter configured for modulating digital data into a multiple-frequency analog signal output;

(b) a demodulation circuit within a receiver configured for demodulating the multiple-frequency analog signal from said transmitter back into digital data;

(c) a transmission controller coupled to said modulation circuit for controlling a phase adjustment cycle between said transmitter and said receiver; and

(d) a phase adjustment controller coupled for receiving outputs from said demodulation circuit and for controlling phase of a phase-locked loop circuit coupled to multiple-frequency mixers in said demodulation circuit;

(e) wherein during a phase adjustment cycle, predefined signal patterns are sent by said transmission controller to said phase adjustment controller, from which an optimum phase adjustment is determined for said phase-locked loop circuit controlling demodulation mixers in said demodulation circuit.

2. The apparatus recited in claim 1, wherein said phase adjustment controller is configured for validating correctness of demodulator output toward achieving maximum recovered signal strength based on performing said phase adjustment cycle.

3. The apparatus recited in claim 1, wherein said phase adjustment cycle is performed periodically toward assuring proper synchronization between transmitter and receiver.

4. The apparatus recited in claim 1, wherein synchronization between modulation and demodulation is achieved without performing digital signal processing (DSP).

5. The apparatus recited in claim 1, wherein phase synchronization is provided, between modulation in the transmitter and demodulation in the receiver, with reduced latency, or reduced power consumption, or a combination of reduced latency and reduced power consumption.

6. The apparatus recited in claim 1, wherein said transmitter and said receiver are located on different integrated circuits which are interconnected.

7. The apparatus recited in claim 6, wherein different integrated circuits are interconnected in response to connection of through-silicon-vias (TSVs) on their respective different integrated circuits which are interconnected.

8. The apparatus recited in claim 1, wherein a phase delay arises due to signal propagation through various elements between modulation in the transmitter of a first integrated circuit and demodulation in the receiver of a second integrated circuit.

9. The apparatus recited in claim 1, wherein said apparatus utilizes quadrature amplitude modulation (QAM) and (QAM) demodulation through-silicon via (TSV) links.

10. The apparatus recited in claim 1:

wherein said transmission controller sends a predefined phase adjust data pattern through DM_TX for receipt by said receiver and its phase adjustment controller;

wherein said transmission controller sends a set of digital codes to the phase adjustment controller to adjust phase delay of a phase lock loop (PLL) in the demodulator of said receiver;

wherein said phase adjustment controller controls phase difference of a mixing carrier for each different digital code, so that said mixing carrier with phase delay is applied to the demodulation mixers in the demodulator;

wherein output data DM_RX from the demodulator is fed back to the phase adjustment controller;

wherein the phase adjustment controller checks if output data DM_RX matches a predefined phase adjust data pattern and records all check comparison results of the phase adjust data pattern; and

wherein the phase adjustment controller compares check comparison results and asserts optimum phase delay to the PLL to maximize recovered signal strength.

11. A method of performing phase synchronization between modulation at a transmitter and demodulation at a receiver, the method comprising:

(a) sending a pre-defined data pattern and a set of digital codes from a transmission controller within a transmitter configured for multiple-frequency modulation of digital data into a multiple-frequency analog output;

(b) receiving said pre-defined data pattern and a set of digital codes at a phase adjustment controller within a receiver configured for demodulation of said multiple-frequency analog output from said transmitter into a digital output;

(c) adjusting phase delay of a phase-lock-loop (PLL) within said phase adjustment controller in response to said pre-defined data pattern and set of digital codes to generate a demodulation carrier to a demodulation mixer within the receiver;

(d) validating correctness of demodulation mixer output for each digital code within said set of digital codes; and

(e) asserting correct phase adjustment within the phase adjustment controller to optimize the demodulation carrier for maximum recovered signal strength of the demodulator after testing all of said set of digital codes, whereby said demodulation in the receiver is then properly synchronized with modulation at the transmitter.

12. The method recited in claim 11, wherein said method provides synchronization without performing digital signal processing (DSP).

13. The method recited in claim 11, wherein said method provides synchronization between modulation and demodulation with reduced latency, or reduced power consumption, or a combination of reduced latency and reduced power consumption.

14. The method recited in claim 11, wherein said transmitter and said receiver are located on different integrated circuits which are interconnected.

15. The method recited in claim 11, wherein different integrated circuits are interconnected in response to connection of through-silicon-vias (TSVs) on their respective different integrated circuits.

16. The method recited in claim 11, wherein a phase delay arises due to signal propagation through various elements between mixers in the transmitter of a first integrated circuit and mixers in the receiver of a second integrated circuit.

17. The method recited in claim 11, wherein said method performs multiple-frequency modulation based on quadrature amplitude modulation (QAM) through-silicon via (TSV) links.

18. A method of performing phase synchronization between modulation at a transmitter and demodulation at a receiver, the method comprising:

(a) sending a pre-defined phase adjust data pattern from a transmission controller of a transmitter to be output from a modulation mixer of the transmitter;

(b) sending a set of digital codes from the transmission controller to a phase adjustment controller of a receiver, said set of digital codes adjust phase delay of a phase lock loop (PLL) in said phase adjustment controller;

(c) controlling phase difference of a mixing carrier of the receiver based on output of said phase lock loop (PLL) for each different digital code in the set of digital codes;

(d) applying mixing carrier with phase delay to a demodulation mixer of the receiver with demodulated output from the demodulation mixer fed back to the phase adjustment controller;

(e) checking demodulated output within the phase adjustment controller for matching with pre-defined phase adjust data and storing results; and

(f) examining stored results after storing data for all pre-defined phase adjust data and selecting optimum phase delay for the PLL, controlling demodulation mixers in said demodulation circuit, to maximize recovered signal strength and thus to phase synchronize demodulation at the receiver with modulation at the transmitter.

19. The method recited in claim 18, wherein said phase adjustment cycle is performed periodically toward assuring proper phase synchronization between transmitter and receiver.

20. The method recited in claim 18, wherein phase synchronization between modulation and demodulation is achieved without digital signal processing (DSP).