Semiconductor device including memory circuit and logic array

• US 9,494,644 B2
• Filed: 11/17/2014
• Issued: 11/15/2016
• Est. Priority Date: 11/22/2013
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Kurokawa, Yoshiyuki
• Primary Examiner(s): Kerveros, James C
• Application Number:
  US14/542,859
• Publication Number:
  US 20150144948A1
• Time in Patent Office: 729 Days
• Field of Search: 714/745
• US Class Current: 1/1
• CPC Class Codes: G01R 31/31707 Test strategies methods for generation of test sequences G01R31/318371
• CPC Class Codes: G01R 31/31723 Hardware for routing the test signal within the device under test to the circuits to be tested, e.g. multiplexer for multiple core testing, accessing internal nodes routing the test signal to or from the device under test G01R31/31926
• CPC Class Codes: G01R 31/31724 Test controller, e.g. BIST state machine for scan test G01R31/318555
• CPC Class Codes: G01R 31/318508 Board Level Test, e.g. P1500 Standard features related to boundary scan G01R31/318533
• CPC Class Codes: G01R 31/3187 Built-in tests
• CPC Class Codes: G06F 11/1407 Checkpointing the instruction stream
• CPC Class Codes: G06F 11/3636 by tracing the execution of the program
• CPC Class Codes: H01L 29/24 including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22 including organic materials H10K99/00
• CPC Class Codes: H01L 29/78618 characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure silicide contacts, electrodes in general H01L29/458
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Abstract

A semiconductor device in which the area of a circuit that is unnecessary during normal operation is small. The semiconductor device includes a first circuit and a second circuit. The first circuit includes a third circuit storing at least one pair of first data including a history of a branch instruction and a first address corresponding to the branch instruction; a fourth circuit comparing a second address of an instruction and the first address; and a fifth circuit selecting the first data of one pair among the at least one pair in accordance with a comparison result. The second circuit includes a plurality of sixth circuits having a function of generating a signal for testing operation of the first circuit in accordance with second data, and a function of storing the at least one pair together with the second circuit after the operation is tested.

Claims

1. A semiconductor device comprising:

a first circuit comprising a first memory; and

a second circuit comprising a second memory and a logic array,

wherein the comprises a first memory is configured to store first data corresponding to a history of a first branch instruction of the first circuit, and

wherein the second memory is configured to store second data for controlling electrical continuity between circuits in the logic array and an output signal with respect to an input signal of the circuits in the logic array to generate a signal for testing an operating state of the first circuit in a test for the operating state of the first circuit, and third data corresponding to a history of a second branch instruction of the first circuit in normal operation after the test.

2. The semiconductor device according to claim 1,

wherein the second memory comprises a first transistor and a second transistor, and

wherein a first terminal of the first transistor is electrically connected to a gate of the second transistor.

3. The semiconductor device according to claim 1,

wherein the second memory comprises a first transistor and a second transistor,

wherein a first terminal of the first transistor is electrically connected to a gate of the second transistor, and

wherein an on/off state of the second transistor is selected according to the second data input through the first transistor.

4. The semiconductor device according to claim 1,

wherein the second memory comprises a first transistor and a second transistor,

wherein a first terminal of the first transistor is electrically connected to a gate of the second transistor, and

wherein the first transistor comprises a channel formation region comprising an oxide semiconductor.

5. The semiconductor device according to claim 1,

wherein the second memory comprises a first transistor and a second transistor,

wherein a first terminal of the first transistor is electrically connected to a gate of the second transistor,

wherein an on/off state of the second transistor is selected according to the second data input through the first transistor, and

wherein the first transistor comprises a channel formation region comprising an oxide semiconductor.

6. The semiconductor device according to claim 1,

wherein the second memory comprises a first transistor and a second transistor,

wherein a first terminal of the first transistor is electrically connected to a gate of the second transistor,

wherein the first transistor comprises a channel formation region comprising an oxide semiconductor, and

wherein the oxide semiconductor comprises at least one of In, Ga, and Zn.

7. The semiconductor device according to claim 1,

wherein the second memory comprises a first transistor and a second transistor,

wherein a first terminal of the first transistor is electrically connected to a gate of the second transistor,

wherein an on/off state of the second transistor is selected according to the second data input through the first transistor,

wherein the first transistor comprises a channel formation region comprising an oxide semiconductor, and

wherein the oxide semiconductor comprises at least one of In, Ga, and Zn.

8. A semiconductor device comprising:

a first circuit comprising a first memory; and

a second circuit comprising a second memory and a logic array,

wherein the first memory is configured to store first data corresponding to a history of a first branch instruction of the first circuit and a first address of the first branch instruction and a comparator circuit comparing an address of an instruction and the first address, and

wherein the second memory is configured to store second data for controlling electrical continuity between circuits in the logic array and an output signal with respect to an input signal of the circuits in the logic array to generate a signal for testing an operating state of the first circuit in a test for the operating state of the first circuit, and third data corresponding to a history of a second branch instruction of the first circuit and a second address of the second branch instruction in normal operation after the test.

9. The semiconductor device according to claim 8,

wherein the second memory comprises a first transistor and a second transistor, and

wherein a first terminal of the first transistor is electrically connected to a gate of the second transistor.

10. The semiconductor device according to claim 8,

wherein the second memory comprises a first transistor and a second transistor,

wherein a first terminal of the first transistor is electrically connected to a gate of the second transistor, and

wherein an on/off state of the second transistor is selected according to the second data input through the first transistor.

11. The semiconductor device according to claim 8,

wherein the second memory comprises a first transistor and a second transistor,

wherein a first terminal of the first transistor is electrically connected to a gate of the second transistor, and

wherein the first transistor comprises a channel formation region comprising an oxide semiconductor.

12. The semiconductor device according to claim 8,

wherein the second memory comprises a first transistor and a second transistor,

wherein a first terminal of the first transistor is electrically connected to a gate of the second transistor,

wherein an on/off state of the second transistor is selected according to the second data input through the first transistor, and

wherein the first transistor comprises a channel formation region comprising an oxide semiconductor.

13. The semiconductor device according to claim 8,

wherein the second memory comprises a first transistor and a second transistor,

wherein a first terminal of the first transistor is electrically connected to a gate of the second transistor,

wherein the first transistor comprises a channel formation region comprising an oxide semiconductor, and

wherein the oxide semiconductor comprises at least one of In, Ga, and Zn.

14. The semiconductor device according to claim 8,

wherein the second memory comprises a first transistor and a second transistor,

wherein a first terminal of the first transistor is electrically connected to a gate of the second transistor,

wherein an on/off state of the second transistor is selected according to the second data input through the first transistor,

wherein the first transistor comprises a channel formation region comprising an oxide semiconductor, and

wherein the oxide semiconductor comprises at least one of In, Ga, and Zn.

15. A semiconductor device comprising:

a first circuit comprising a first memory; and

a second circuit comprising a second memory and a logic array,

wherein the first memory is configured to store first data corresponding to a history of a first branch instruction of the first circuit and a first address of the first branch instruction, a comparator circuit comparing an address of an instruction and the first address, and a selector circuit selecting the first address in accordance with a comparison result of the comparator circuit, and

wherein the second memory is configured to store second data for controlling electrical continuity between circuits in the logic array and an output signal with respect to an input signal of the circuits in the logic array to generate a signal for testing an operating state of the first circuit in a test for the operating state of the first circuit, and third data corresponding to a history of a second branch instruction of the first circuit and a second address of the second branch instruction in normal operation after the test.

16. The semiconductor device according to claim 15,

wherein the second memory comprises a first transistor and a second transistor, and

wherein a first terminal of the first transistor is electrically connected to a gate of the second transistor.

17. The semiconductor device according to claim 15,

wherein the second memory comprises a first transistor and a second transistor,

wherein a first terminal of the first transistor is electrically connected to a gate of the second transistor, and

wherein an on/off state of the second transistor is selected according to the second data input through the first transistor.

18. The semiconductor device according to claim 15,

wherein the second memory comprises a first transistor and a second transistor,

wherein a first terminal of the first transistor is electrically connected to a gate of the second transistor, and

wherein the first transistor comprises a channel formation region comprising an oxide semiconductor.

19. The semiconductor device according to claim 15,

wherein the second memory comprises a first transistor and a second transistor,

wherein a first terminal of the first transistor is electrically connected to a gate of the second transistor,

wherein an on/off state of the second transistor is selected according to the second data input through the first transistor, and

wherein the first transistor comprises a channel formation region comprising an oxide semiconductor.

20. The semiconductor device according to claim 15,

wherein the second memory comprises a first transistor and a second transistor,

wherein a first terminal of the first transistor is electrically connected to a gate of the second transistor,

wherein the first transistor comprises a channel formation region comprising an oxide semiconductor, and

wherein the oxide semiconductor comprises at least one of In, Ga, and Zn.

21. The semiconductor device according to claim 15,

wherein the second memory comprises a first transistor and a second transistor,

wherein a first terminal of the first transistor is electrically connected to a gate of the second transistor,

wherein an on/off state of the second transistor is selected according to the second data input through the first transistor,

wherein the first transistor comprises a channel formation region comprising an oxide semiconductor, and

wherein the oxide semiconductor comprises at least one of In, Ga, and Zn.