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TN liquid crystal display device and touch control method thereof

  • US 9,494,815 B2
  • Filed: 11/20/2013
  • Issued: 11/15/2016
  • Est. Priority Date: 12/24/2012
  • Status: Active Grant
First Claim
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1. A twisted nematic liquid crystal display device integrated with a touch control function, the device comprising:

  • an array substrate;

    a color film substrate disposed opposite the array substrate;

    a liquid crystal layer disposed between the array substrate and the color film substrate; and

    a common electrode layer disposed on a surface of the color film substrate facing the liquid crystal layer, wherein the common electrode layer comprises;

    a plurality of sensing electrodes,a plurality of driving electrodes,a plurality of dummy electrodes located between the sensing electrodes and the driving electrodes, wherein the sensing electrodes, the driving electrodes, and the dummy electrodes are insulated from one another;

    a black matrix layer located between the color film substrate and the common electrode layer, wherein the sensing electrodes, the driving electrodes and the dummy electrodes are isolated and insulated from each other by gaps in the common electrode layer, and the gaps are covered by the black matrix layer;

    a gate electrode layer disposed on a surface of the array substrate facing the liquid crystal layer, wherein the gate electrode layer comprises gate electrodes and scanning lines;

    a first insulating layer disposed on the gate electrode layer;

    a silicon island disposed on the first insulating layer;

    a source/drain electrode layer disposed on the silicon island, wherein the source/drain electrode layer comprises source electrodes, drain electrodes and data lines,wherein the gate electrode within the gate electrode layer, the first insulating layer, the silicon island, the source electrode, and the drain electrode collectively form a thin film transistor structure;

    a second insulating layer disposed on the source/drain electrode layer;

    a third insulating layer disposed on the second insulating layer;

    a pixel electrode layer disposed on the third insulating layer;

    a first transparent electrode layer disposed between the first insulating layer and the gate electrode layer, wherein the first transparent electrode layer covers the scanning lines of the gate electrode layer and does not cover an area of the gate electrodes at the gate electrode layer; and

    a fourth insulating layer disposed between the first transparent electrode layer and the gate electrode layer.

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