Trigger circuits and event counters for an IC
First Claim
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1. A method of controlling a clock of an integrated circuit (“
- IC”
) comprising a plurality of groups of configurable circuits for configurably performing operations of a user design based on configuration data, said method comprising;
commencing operation of said IC based on said clock; and
at a particular clock cycle of said clock;
adjusting a clock control value stored in a storage element located on a same IC die as said groups of configurable circuits;
determining whether the clock control value is equal to a predetermined value; and
upon determining that the clock control value is equal to a predetermined value, halting said clock in order to allow one or more of said groups of configurable circuits to be accessed, wherein said adjusting, determining, and halting are performed by clock control circuitry on the same IC substrate as the configurable circuits, and wherein the clock control circuitry comprises a clock control circuit, a counter, and a logic gate.
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Abstract
Some embodiments provide an integrated circuit (“IC”). The IC includes multiple configurable circuits that configurably perform operations of a user design based on configuration data. The IC also includes a configurable trigger circuit that receives a set of configuration data that specifies an operational event. The configurable trigger circuit also determines whether the operational event has occurred during implementation of the user design of the IC. Additionally, the operational trigger event outputs a trigger signal upon determining that the operational trigger event has occurred.
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Citations
14 Claims
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1. A method of controlling a clock of an integrated circuit (“
- IC”
) comprising a plurality of groups of configurable circuits for configurably performing operations of a user design based on configuration data, said method comprising;commencing operation of said IC based on said clock; and at a particular clock cycle of said clock; adjusting a clock control value stored in a storage element located on a same IC die as said groups of configurable circuits; determining whether the clock control value is equal to a predetermined value; and upon determining that the clock control value is equal to a predetermined value, halting said clock in order to allow one or more of said groups of configurable circuits to be accessed, wherein said adjusting, determining, and halting are performed by clock control circuitry on the same IC substrate as the configurable circuits, and wherein the clock control circuitry comprises a clock control circuit, a counter, and a logic gate. - View Dependent Claims (2, 3, 4, 5, 6)
- IC”
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7. A method of controlling a plurality of clocks of an integrated circuit (“
- IC”
) comprising a clock control circuit, said method comprising;operating said IC based on said plurality of clocks; adjusting a clock counter; and outputting, from the clock control circuit, a signal that halts a first clock of said plurality of clocks when the clock counter reaches a predetermined value, wherein said halting of the first clock causes one or more other clocks of the plurality of clocks to halt. - View Dependent Claims (9)
- IC”
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8. The method of 7, wherein the IC further comprises a plurality of configurable circuits that each operate based on one of said clocks, wherein halting a particular clock halts the configurable circuits that operate based on the halted particular clock.
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10. A method of debugging an integrated circuit (“
- IC”
) comprising (i) a user clock, wherein each cycle of said user clock comprises a plurality of sub-cycles, and (ii) a debug clock, wherein said debug clock is asynchronous with said user clock, said method comprising;receiving a plurality of sets of user design state (“
UDS”
) values, wherein each of said sets of UDS values is received at a different sub-cycle of the user clock;storing each of said plurality of sets of UDS values for more than one sub-cycle of said user clock; adjusting a clock counter; using clock control circuitry to determine when the clock counter has reached a predetermined value to determine edges of the debug clock; and in response to determining edges of the debug clock, reading each stored set of UDS values. - View Dependent Claims (11, 12, 13, 14)
- IC”
Specification