System managing a plurality of flash memory devices

• US 9,495,105 B2
• Filed: 01/07/2016
• Issued: 11/15/2016
• Est. Priority Date: 09/01/2005
• Status: Active Grant

• Current Assignee: Hitachi, Ltd.
• Original Assignee: Hitachi, Ltd.
• Inventors: Nakamura, Shuji, Fujimoto, Kazuhisa, Fujibayashi, Akira
• Primary Examiner(s): THAI, TUAN V
• Application Number:
  US14/989,965
• Publication Number:
  US 20160179380A1
• Time in Patent Office: 313 Days
• Field of Search: 711/100, 711/103, 711/11, 711/112, 711/135, 711/154, 711/200, 711/111, 711/113
• US Class Current: 1/1
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/0802 Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
• CPC Class Codes: G06F 12/0866 for peripheral storage systems, e.g. disk cache
• CPC Class Codes: G06F 2212/1044 Space efficiency improvement
• CPC Class Codes: G06F 2212/2022 Flash memory
• CPC Class Codes: G06F 2212/263 Network storage, e.g. SAN or NAS
• CPC Class Codes: G06F 2212/314 In storage network, e.g. network attached cache
• CPC Class Codes: G06F 2212/60 Details of cache memory
• CPC Class Codes: G06F 2212/7211 Wear leveling
• CPC Class Codes: G06F 3/061 Improving I/O performance
• CPC Class Codes: G06F 3/0626 Reducing size or complexity of storage systems
• CPC Class Codes: G06F 3/0649 Lifecycle management
• CPC Class Codes: G06F 3/0658 Controller construction arrangements
• CPC Class Codes: G06F 3/067 Distributed or networked storage systems, e.g. storage area networks [SAN], network attached storage [NAS]
• CPC Class Codes: G06F 3/0685 Hybrid storage combining heterogeneous device types, e.g. hierarchical storage, hybrid arrays
• CPC Class Codes: G06F 3/0688 Non-volatile semiconductor memory arrays
• CPC Class Codes: G06F 3/0689 Disk arrays, e.g. RAID, JBOD
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A system includes a plurality of flash memory devices, a processor configured to control read/write requests, and a cache memory configured to store data temporarily. The processor is configured to, according to a read request for first data from a read/write data source, when the first data is not stored within the cache memory, transfer the first data requested by the read request from one of the plurality of flash memory devices to the read/write data source without storing the first data in the cache memory, and according to a write request from the read/write data source, store second data requested by the write request in the cache memory

Claims

1. A system comprising:

a plurality of flash memory devices; and

a processor configured to control read/write requests,

a cache memory configured to store data temporarily,

wherein the processor is configured to;

according to a read request for first data from a read/write request source, when the first data is not stored within the cache memory, transfer the first data requested by the read request from one of the plurality of flash memory devices to the read/write request source without storing the first data in the cache memory, and

according to a write request from the read/write request source, store second data requested by the write request in the cache memory.

2. A system according to claim 1,

wherein the read/write request source is a computer coupled to the system.

3. A system according to claim 1,

wherein each of the plurality of flash memory devices includes a plurality of flash memory chips, and

wherein a wear leveling process is performed in the each of the plurality of flash memory devices.

4. A system according to claim 1,

wherein the plurality of flash memory devices is configured as a RAID (Redundant Array of Independent Disks) group.

5. A system according to claim 1,

wherein the cache memory is a volatile memory.

6. A system comprising:

a processor configured to manage storage regions based on a plurality of flash memory devices,

a cache memory configured to store data temporarily,

wherein the processor is configured to;

according to a read request for first data from a read/write request source, when the first data is not stored within the cache memory, transfer the first data requested by the read request from the storage regions based on the plurality of flash memory devices to the read/write request source without storing the first data in the cache memory, and

according to a write request from the read/write request source, store second data requested by the write request in the cache memory.

7. A system according to claim 6,

wherein the read/write request source is a computer coupled to the system.

8. A system according to claim 6,

wherein each of the plurality of flash memory devices includes a plurality of flash memory chips, and

wherein a wear leveling process is performed in the each of the plurality of flash memory devices.

9. A system according to claim 6,

wherein the plurality of flash memory devices is configured as a RAID (Redundant Array of Independent Disks) group.

10. A system according to claim 6,

wherein the cache memory is a volatile memory.