Various methods and apparatus to support outstanding requests to multiple targets while maintaining transaction ordering

• US 9,495,290 B2
• Filed: 06/24/2008
• Issued: 11/15/2016
• Est. Priority Date: 06/25/2007
• Status: Active Grant

• Current Assignee: META Platforms Technologies LLC (Meta Platforms, Inc. (f/k/a Facebook, Inc.))
• Original Assignee: Sonics Incorporated (Meta Platforms, Inc. (f/k/a Facebook, Inc.))
• Inventors: Wingard, Drew E., Chou, Chien-Chun, Hamilton, Stephen W., Swarbrick, Ian Andrew, Vakilotojar, Vida
• Primary Examiner(s): Bullock, Jr., Lewis A
• Assistant Examiner(s): Lu, Kevin X
• Application Number:
  US12/144,987
• Publication Number:
  US 20080320476A1
• Time in Patent Office: 3,066 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: G06F 12/0607 Interleaved addressing
• CPC Class Codes: G06F 15/17375 One dimensional, e.g. linear array, ring
• CPC Class Codes: G11C 7/1072 for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A method, apparatus, and system are described, which generally relate to an integrated circuit having an interconnect that implements internal controls. The interconnect in an integrated circuit communicates transactions between initiator Intellectual Property (IP) cores and target IP cores coupled to the interconnect. The interconnect implements logic configured to support multiple transactions issued from a first initiator IP core to the multiple target IP cores while maintaining an expected execution order within the transactions. The logic supports a second transaction to be issued from the first initiator IP core to a second target IP core before a first transaction issued from the same first initiator IP core to a first target IP core has completed while ensuring that the first transaction completes before the second transaction and while ensuring an expected execution order within the first transaction and second transaction are maintained. The logic does not include any reorder buffering.

Claims

1. An interconnect, the interconnect configured to allow for an integrated circuit to communicate transactions between one or more initiator Intellectual Property (IP) cores and multiple target IP cores coupled to the interconnect, wherein the interconnect implements logic distributed over the interconnect and configured to support multiple transactions issued from a first initiator IP core to the multiple target IP cores while maintaining an expected execution order within the transactions, wherein the logic supports a second transaction to be issued from the first initiator IP core to a second target IP core before a first transaction issued from the first initiator IP core to a first target IP core has completed while ensuring that the first transaction completes before the second transaction completes, where the logic does not include any reorder buffering, and while ensuring the expected execution order within the first transaction and second transaction are maintained.

2. The interconnect of claim 1, wherein the first and second transactions are part of a same thread from the first initiator IP core, and the expected execution order within the first transaction is independent of ordering of other threads.

3. The interconnect of claim 1, wherein the first and second transactions are each composed of one or more requests and one or more optional responses, and an aggregate target IP core of the multiple target IP cores includes two or more memory channels that are interleaved in an address space for an aggregate target in an address map.

4. The interconnect of claim 1, wherein the logic is configured to support one or more transactions issued from a second initiator IP core to at least the first target IP core, simultaneous with the multiple transactions issued from the first initiator IP core to the first and second target IP cores while maintaining the expected execution order for all of the transactions and thereby allowing transactions from several initiators to be outstanding simultaneously to several targets.

5. The interconnect of claim 3, wherein the flow control logic is associated with a thread splitter unit in a request path to a destination address of a target IP core and the thread splitter unit implements flow control to prevent an issuance of a next request from a same thread from the first initiator IP core headed to a first physical pathway, other than a second physical pathway currently being used by outstanding requests in that same thread until all acknowledge notifications from outstanding requests in that same thread going to the second physical pathway are communicated back to the thread splitter unit.

6. The interconnect of claim 5, wherein the flow control logic to track the acknowledge notifications from requests within the same thread, indicating safe arrival of those requests, to ensure all previous requests headed toward an intended target have reached a last thread merger unit prior to the intended target before requests from the same thread are routed along a separate physical path to second intended target.

7. The interconnect of claim 5, wherein the flow control logic associated with the thread splitter unit that split a set of transactions in that given thread issues the next request being routed down the separate first physical pathway from other outstanding requests in that thread 1) no earlier than one cycle after an amount of words in an immediate previous request if the previous request was a burst request or 2) no earlier than a sum of a total time of an amount of time the immediate previous request will arrive at a last thread merger unit prior to that previous request'"'"'s target address plus an amount of time to communicate the acknowledgement notification back to the thread splitter unit.

8. The interconnect of claim 3, wherein the interconnect also implements flow control protocol internal to the interconnect in a response network to enforce ordering restrictions of when to return responses within a same thread to correspond to an order in which the requests triggering the responses were transmitted, and the flow control protocol is non-blocking with respect to requests from another thread, and

the flow control logic internal to the interconnect interrogates the address map and a known structural organization of a first aggregated target in the integrated circuit to decode an interleaved address space of the aggregated target to determine physical distinctions between the target IP cores making up the first aggregated target in order to determine which targets making up the first aggregated target need to service a first request.

9. The interconnect of claim 2, wherein the flow control logic applies a flow control splitting protocol to allow multiple transactions from the same thread to be outstanding to multiple channels of an aggregated target at any given time and the multiple channels in an aggregated target map to IP memory cores having physically different addresses and an ordered flow queue exists per received thread in a thread splitter unit as well as a table to locally maintain a history of requests in each ordered flow queue.

10. The interconnect of claim 3, wherein the interconnect is part of a System-on-a-Chip that is pipelined to store and move requests and responses in stages through the System-on-a-Chip and the flow control logic is non-blocking with respect to requests from another thread as well as with respect to requiring a response to a first request before issuing a second request from the same thread, pipelined, and maintains each thread'"'"'s execution order.

11. The interconnect of claim 2, wherein the interconnect contains a first thread splitting unit cascaded in a request path with a second thread splitting unit.

12. A non-transitory machine-readable medium having data and instructions stored thereon, which, when executed by a machine, cause the machine to generate a representation of the apparatus of claim 1.

13. The non-transitory machine-readable medium of claim 12, wherein the machine-readable medium stores an Electronic Design Automation (EDA) toolset used in a System-on-a-Chip design process that has the data and instructions to generate the representation of the apparatus.

14. A method, comprising:

maintaining an expected execution order of a set of transactions in a thread that are issued by an initiator Intellectual Property core across an interconnect to a target Intellectual Property core by use of flow control logic in a thread splitter unit internal to and distributed over the interconnect that allows received requests from a given thread to be outstanding at any given time but restricts an issuance of a subsequent request from that thread having a destination address down a separate physical pathway from all of the outstanding requests in that thread;

establishing a local order of received requests at the thread splitter unit; and

maintaining the local order of received requests in one of the threads to compare the received requests to other requests in that same thread to ensure the subsequent request to the separate physical pathway is not released from the thread splitter unit until all earlier requests from that same thread going to an initial physical pathway have communicated acknowledge signals back to the thread splitter unit.

15. The method of claim 14, further comprising:

restricting the issuance of the subsequent request until

     1) no earlier than one cycle after an amount of words in an immediate previous request if the previous request was a burst request or

     2) no earlier than a sum of a total time of an amount of anticipated time the immediate previous request will arrive at a last thread merger point prior to a target address of the immediate previous request plus an amount of time to communicate an acknowledgement notification indicating safe arrival of the immediate previous request back to the thread splitter unit.

16. The method of claim 14, further comprising:

continuously sending requests from the given thread from an upstream thread splitter unit to a downstream thread splitter unit until the subsequent request needs to be split down the separate physical pathway at the downstream thread splitter unit, wherein the downstream thread splitter unit implements flow control buffering of the subsequent request from the same thread heading down the separate physical pathway than all of the outstanding requests from that thread until all of the outstanding requests from that thread headed down the initial physical pathway have communicated an acknowledge notification of receipt of those outstanding requests to the downstream thread splitter unit causing the pathway splitting.

17. The method of claim 16, wherein the acknowledge notification is implied and thereby negates a return of an actual acknowledge notification for a request in both situations 1) if no thread splitter units exist between an initial thread splitter unit and a last thread merger unit prior to the final destination address of the request and 2) if no other thread affecting components exist between the initial thread splitter unit and the downstream thread splitter unit.

18. A machine-readable medium having data and instructions stored thereon, which, when executed by a machine, cause the machine to perform the operations in claim 15, wherein the machine-readable medium stores an Electronic Design Automation (EDA) toolset used in a System-on-a-Chip design process that has the data and instructions to perform the operations in claim 15.

19. An Integrated Circuit, comprising:

multiple initiator IP cores;

multiple target IP cores including memory IP cores;

an interconnect to communicate requests as well as responses to those requests between the multiple initiator IP cores and the multiple target IP cores coupled to the interconnect; and

flow control logic internal to and distributed over the interconnect to maintain an expected execution order of a set of transactions in a thread that are issued by a first initiator IP core across the interconnect to a first target IP core, wherein the flow control logic allows multiple requests from a given thread to be outstanding at any given time but restricts an issuance of a subsequent request from that thread having a destination address down a separate physical pathway from all of the outstanding requests in that thread.

20. The Integrated Circuit of claim 19, wherein the flow control logic to track acknowledge notifications from requests within the same thread, indicating safe arrival of those requests, to ensure all previous requests headed toward the first target IP core have reached a last thread merger unit prior to the first target IP core before requests from the same thread are routed down the separate physical pathway to a second target, and the flow control logic internal to the interconnect interrogates an address map and a known structural organization of an aggregated target in the Integrated Circuit to decode an interleaved address space of the aggregated target to determine physical distinctions between the targets making up the aggregated target in order to determine which of the target IP cores making up the first aggregated target need to service a first request.