Universal inter-layer interconnect for multi-layer semiconductor stacks

• US 9,495,498 B2
• Filed: 09/14/2012
• Issued: 11/15/2016
• Est. Priority Date: 04/28/2009
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: GlobalFoundries, Inc.
• Inventors: Bartley, Gerald K., Hoover, Russell Dean, Johnson, Charles Luther, VanderWiel, Steven Paul, Varekamp, Patrick Ronald
• Primary Examiner(s): Crawford, Jason M
• Assistant Examiner(s): Bahr, Kurtis R
• Application Number:
  US13/618,600
• Publication Number:
  US 20130009324A1
• Time in Patent Office: 1,523 Days
• Field of Search: 326/37, 326 41- 47, 326/101, 257/686, 257/698, 257/692, 257/E23.174, 257/E21.585, 257/E21.597, 257/208, 438/109, 438/667
• US Class Current: 1/1
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347
• CPC Class Codes: H01L 2224/05001 Internal layers
• CPC Class Codes: H01L 2224/05009 Bonding area integrally formed with a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05099 Material
• CPC Class Codes: H01L 2224/05568 the whole external layer protruding from the surface
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01019 Potassium [K]
• CPC Class Codes: H01L 2924/01087 Francium [Fr]

Abstract

An apparatus, program product and method facilitate the design of a multi-layer circuit arrangement incorporating a universal, standardized inter-layer interconnect in a multi-layer semiconductor stack to facilitate interconnection and communication between functional units disposed on a stack of semiconductor dies. Each circuit layer in the multi-layer semiconductor stack is required to include an inter-layer interface region that is disposed at substantially the same topographic location such that when the semiconductor dies upon which such circuit layers are disposed are arranged together in a stack, electrical conductors disposed within each semiconductor die are aligned with one another to provide an inter-layer bus that is oriented vertically, or transversely, with respect to the individual circuit layers.

Claims

1. A circuit arrangement, comprising:

a plurality of semiconductor dies physically and electrically coupled to one another in a stack, the plurality of semiconductor dies including at least three dies, each semiconductor die including opposing faces, wherein at least one face of each semiconductor die includes circuit logic integrated thereon and defining a circuit layer that includes at least one functional unit, wherein at least one face of each semiconductor die includes a standardized inter-layer interface region disposed thereon, and wherein each inter-layer interface region on each semiconductor die is disposed at substantially the same topographic location when the respective semiconductor die is disposed within the stack;

a first inter-layer bus electrically coupling the functional units on the plurality of semiconductor dies to one another, the first inter-layer bus comprising a plurality of electrical conductors disposed within the inter-layer interface region of each semiconductor die and extending between the opposing faces of each semiconductor die, wherein respective electrical conductors disposed in the inter-layer interface regions of adjacent semiconductor dies in the stack are electrically coupled to one another when the plurality of circuit layers are physically and electrically coupled to one another in the stack; and

a second inter-layer bus topographically separated from the first inter-layer bus,

wherein the stack of semiconductor dies defines first and second vertically-oriented supernodes, wherein the circuit layers on multiple semiconductor dies in the stack include functional units allocated to each of the first and second supernodes, with the functional units allocated to the first supernode coupled to the first inter-layer bus and the functional units allocated to the second supernode coupled to the second inter-layer bus, and

wherein each semiconductor die includes a regular array of contact pads disposed on at least one face of such semiconductor die, wherein the plurality of electrical conductors disposed within the inter-layer interface region of such semiconductor die and extending between the opposing faces of each semiconductor die are topographically aligned and electrically coupled to at least a first subset of the regular array of contact pads that are topographically disposed within the inter-layer interface region of such semiconductor die.

2. The circuit arrangement of claim 1, wherein the plurality of electrical conductors in each semiconductor die comprises a plurality of functional bus conductors and a plurality of pervasive interconnects, and wherein the plurality of functional bus conductors define a command bus and a data bus.

3. The circuit arrangement of claim 2, wherein the plurality of pervasive interconnects includes at least one pervasive interconnect selected from the group consisting of an LBIST interconnect, an ABIST interconnect, a trace interconnect, a performance monitor interconnect, a reset interconnect, an error status interconnect, an interrupt interconnect, and a clock interconnect.

4. The circuit arrangement of claim 1, wherein the topographic locations of the electrical conductors disposed within each inter-layer interface region are substantially the same for each inter-layer interface region on each semiconductor die.

5. The circuit arrangement of claim 1, wherein at least one semiconductor die in the stack has different topographic dimensions from another semiconductor die in the stack.

6. The circuit arrangement of claim 1, wherein at least one semiconductor die in the stack is fabricated using different semiconductor fabrication design rules from another semiconductor die in the stack.

7. The circuit arrangement of claim 1, wherein the circuit layer on at least one semiconductor die defines a compute layer including at least one processor functional unit and the circuit layer on at least one semiconductor die defines an accelerator layer including at least one accelerator functional unit.

8. The circuit arrangement of claim 7, wherein the circuit layer on at least one semiconductor die defines an I/O layer, the I/O layer including a memory controller functional unit and at least one external interface functional unit, each of the memory controller and external interface functional units coupled to external interfaces to interface the plurality of semiconductor dies with at least one external device.

9. The circuit arrangement of claim 1, wherein the first inter-layer bus comprises a plurality of bus segments extending through the plurality of semiconductor dies, each bus segment disposed at a different topographical location, and wherein the circuit layer in at least one semiconductor die includes an intra-layer bus disposed in the circuit logic thereof and electrically coupling the plurality of bus segments to one another.

10. The circuit arrangement of claim 1, wherein at least a second subset of the regular array of contact pads that are disposed outside of the inter-layer interface region of such semiconductor die define a power distribution network for the circuit layer on such semiconductor die.

11. The circuit arrangement of claim 1, wherein the plurality of conductors in at least one semiconductor die includes a plurality of conductive through vias extending through the semiconductor die.

12. The circuit arrangement of claim 1, wherein each semiconductor die in the stack has substantially the same topographic dimensions.

13. The circuit arrangement of claim 1, wherein each semiconductor die in the stack is fabricated using substantially the same semiconductor fabrication design rules.

14. The circuit arrangement of claim 1, wherein the circuit layer in at least one semiconductor die further comprises an intra-layer bus disposed in the circuit logic thereof to electrically couple each functional unit disposed in such circuit layer to the first inter-layer bus, wherein the intra-layer bus includes a plurality of electrical conductors that are coupled to corresponding electrical conductors in the first inter-layer bus.

15. A circuit arrangement, comprising:

a plurality of semiconductor dies physically and electrically coupled to one another in a stack, the plurality of semiconductor dies including at least three dies, each semiconductor die including opposing faces, wherein at least one face of each semiconductor die includes circuit logic integrated thereon and defining a circuit layer that includes at least one functional unit, wherein at least one face of each semiconductor die includes a standardized inter-layer interface region disposed thereon, and wherein each inter-layer interface region on each semiconductor die is disposed at substantially the same topographic location when the respective semiconductor die is disposed within the stack; and

an inter-layer bus electrically coupling the functional units on the plurality of semiconductor dies to one another, the inter-layer bus comprising a plurality of electrical conductors disposed within the inter-layer interface region of each semiconductor die and extending between the opposing faces of each semiconductor die, wherein respective electrical conductors disposed in the inter-layer interface regions of adjacent semiconductor dies in the stack are electrically coupled to one another when the plurality of circuit layers are physically and electrically coupled to one another in the stack,

wherein each semiconductor die includes a standardized, regular array of contact pads disposed on at least one face of such semiconductor die, wherein the plurality of electrical conductors disposed within the inter-layer interface region of such semiconductor die and extending between the opposing faces of each semiconductor die are topographically aligned and electrically coupled to at least a first subset of the regular array of contact pads that are topographically disposed within the inter-layer interface region of such semiconductor die,

wherein at least a second subset of the regular array of contact pads that are disposed outside of the inter-layer interface region of such semiconductor die define a power distribution network for the circuit layer on such semiconductor die, and

wherein a contact pad pitch for the contact pads electrically coupled to the inter-layer bus is greater than that for the contact pads electrically coupled to the power distribution network, and wherein at least a third subset of the regular array of contact pads that are disposed outside of the inter-layer interface region of such semiconductor die are dummy contact pads.

16. The circuit arrangement of claim 15, wherein the contact pad pitch for the contact pads electrically coupled to the inter-layer bus is about three times that for the contact pads electrically coupled to the power distribution network.