Method for integrated circuit mask patterning

• US 9,495,507 B2
• Filed: 02/08/2016
• Issued: 11/15/2016
• Est. Priority Date: 02/13/2014
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Yu, Jue-Chin, Hsieh, Lun, Chen, Pi-Tsung, Chou, Shuo-Yen, Liu, Ru-Gun
• Primary Examiner(s): Levin, Naum B
• Application Number:
  US15/018,390
• Publication Number:
  US 20160154925A1
• Time in Patent Office: 281 Days
• US Class Current: 1/1
• CPC Class Codes: G03F 1/36 Masks having proximity correction features; Preparation thereof, e.g. optical proximity correction [OPC] design processes
• CPC Class Codes: G03F 1/70 Adapting basic layout or design of masks to lithographic process requirements, e.g., second iteration correction of mask patterns for imaging
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36

Abstract

Provided is a method of transforming an integrated circuit (IC) pattern into one or more patterns suitable for subsequent processing, such as mask fabrication. The method includes receiving an IC pattern that has an arbitrary shape, and using a computer, deriving an approximation IC pattern that is a user-defined fabrication-friendly shape, such as a rectangle or an ellipse. The method further includes calculating a pattern approximation error between the IC pattern and the approximation IC pattern. The method further includes checking whether the pattern approximation error is less than a user-defined threshold. If it is, the method further includes replacing the IC pattern with the approximation IC pattern for subsequent fabrication. Otherwise, the method further includes splitting the IC pattern into subparts, and recursively transforming each of the subparts.

Claims

1. A method, comprising the steps of:

providing an integrated circuit (IC) design layout, the IC design layout having a first IC pattern that is not in one of predefined shapes;

using a computer, deriving a second IC pattern approximating the first IC pattern, wherein the second IC pattern is in one of the predefined shapes;

calculating a pattern approximation error between the first IC pattern and the second IC pattern; and

upon a condition in which the pattern approximation error is less than a threshold, replacing the first IC pattern with the second IC pattern in the IC design layout.

2. The method of claim 1, further comprising:

upon a condition in which the pattern approximation error is not less than the threshold, performing the steps of;

splitting the first IC pattern into first IC sub-patterns; and

transforming each of the first IC sub-patterns that is not in one of the predefined shapes by performing the steps of deriving, calculating, conditionally replacing, conditionally splitting, and conditionally transforming.

3. The method of claim 2, wherein the steps of deriving and conditionally transforming produce a plurality of patterns that collectively approximate the first IC pattern.

4. The method of claim 3, further comprising:

connecting the plurality of patterns.

5. The method of claim 1, wherein the pattern approximation error is a normalized pattern error.

6. The method of claim 1, wherein the calculating of the pattern approximation error includes:

determining a center of mass of the first IC pattern; and

upon a condition in which the center of mass is outside of the first IC pattern, deeming the pattern approximation error being greater than the threshold.

7. The method of claim 1, wherein the predefined shapes include a rectangle.

8. The method of claim 1, wherein the predefined shapes include an ellipse.

9. The method of claim 1, wherein the second IC pattern has about the same area as the first IC pattern.

10. The method of claim 1, further comprising, before the deriving of the second IC pattern:

using a computer, determining a center of mass of the first IC pattern; and

upon a condition in which the center of mass is outside of the first IC pattern, separating the first IC pattern into first IC pattern subsets,

wherein the steps of deriving, calculating, and conditionally replacing are performed on each of the first IC pattern subsets.

11. A method, comprising:

providing an integrated circuit (IC) pattern that is not a rectangular shape;

using a computer, determining a rectangle approximating the IC pattern, wherein the rectangle and the IC pattern share a center of mass;

calculating a pattern approximation error between the rectangle and the IC pattern; and

when the pattern approximation error is less than a user-defined threshold, accepting the rectangle as a replacement of the IC pattern in subsequent IC fabrication.

12. The method of claim 11, further comprising:

when the pattern approximation error is greater than or equal to the user-defined threshold, performing the steps of;

splitting the IC pattern into subparts; and

converting each of the subparts that is not already a rectangular shape into at least one rectangle by recursively performing the steps of determining, calculating, conditionally splitting, and conditionally converting.

13. The method of claim 12, wherein the steps of determining and converting produce a plurality of rectangles, further comprising:

connecting the plurality of rectangles to form a continuous shape.

14. The method of claim 12, wherein all sides of the at least one rectangle are oriented along one of two directions:

a first direction and a second direction that is perpendicular to the first direction.

15. The method of claim 12, wherein all sides of the at least one rectangle are oriented along one of four directions:

(1) a first direction, (2) a second direction that is perpendicular to the first direction, (3) a third direction that forms a 45 degree angle with the first direction, and (4) a fourth direction that is perpendicular to the third direction.

16. The method of claim 12, wherein the splitting of the IC pattern is along a direction that is in parallel with a shorter side of the rectangle and across the center of mass.

17. The method of claim 11, further comprising:

outputting vertices of the rectangle in a computer-readable format.

18. A method, comprising the steps of:

receiving an integrated circuit (IC) design layout, the IC design layout having a first pattern that is not in fabrication-friendly shapes;

using a computer, determining a second pattern approximating the first pattern, wherein the second pattern is in the fabrication-friendly shapes;

calculating a deviation between the first pattern and the second pattern; and

upon a condition in which the deviation is greater than a threshold, performing the steps of;

splitting the first pattern into subparts; and

for each of the subparts, recursively performing the steps of determining, calculating, and conditionally splitting.

19. The method of claim 18, further comprising:

upon another condition in which the deviation is not greater than the threshold, replacing the first pattern with the second pattern in the IC design layout.

20. The method of claim 18, wherein the fabrication-friendly shapes include rectangles, ellipses, or a combination thereof.