Tunable negative bitline write assist and boost attenuation circuit

• US 9,496,025 B2
• Filed: 01/12/2015
• Issued: 11/15/2016
• Est. Priority Date: 01/12/2015
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Chandra, Dinesh, Potladhurthi, Eswararao, Reddy, Dhani Reddy Sreenivasula, Rengarajan, Krishnan S.
• Primary Examiner(s): Sofocleous, Alexander
• Assistant Examiner(s): BERMUDEZ LOZADA, ALFREDO
• Application Number:
  US14/594,673
• Publication Number:
  US 20160203857A1
• Time in Patent Office: 673 Days
• Field of Search: 365/154, 365/189.2, 365/189.16
• US Class Current: 1/1
• CPC Class Codes: G11C 11/412 using field-effect transistors only
• CPC Class Codes: G11C 11/419 Read-write [R-W] circuits
• CPC Class Codes: G11C 7/12 Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines

Abstract

An apparatus and method are provided for implementing write assist with boost attenuation for static random access memory (SRAM) arrays. The apparatus includes a memory array comprising a plurality of SRAM cells. The apparatus further includes a write driver connected to each of a differential pair of bit lines in each of the plurality of SRAM cells of the memory array. The apparatus further includes a write assist attenuation circuit connected to the write driver, the write assist attenuation circuit comprising a clamping device configured to modify a control signal as a function of supply voltage and process to attenuate an amount of boost applied to pull one of the bit lines below ground in an active phase of a write cycle.

Claims

1. A device, comprising:

a memory array comprising a plurality of static random access memory (SRAM) cells;

a plurality of true bit lines each connected to a column of the memory array;

a plurality of complement bit lines each forming a differential pair with, and in a same column as, one of the plurality of true bit lines;

a write driver connected to each of the differential pair of bit lines in each of the plurality of SRAM cells of the memory array, the write driver comprising;

a negative boost node;

discharge device coupled to ground and the negative boost node, the discharge device configured to receive a control signal and pull one of the plurality of true bit lines or one of the plurality of complement bit lines to ground in an active phase of a write cycle; and

a boost capacitor coupled to the negative boost node, the boost capacitor configured to boost the one of the plurality of true bit lines or the one of the plurality of complement bit lines below ground; and

a write assist attenuation circuit connected to the discharge device, the write assist attenuation circuit comprising a clamping device configured to modify the control signal as a function of supply voltage and process to attenuate an amount of the boost,

wherein the clamping circuit includes a first NFET and a second NFET,

wherein a source of the first NFET is connected to the control signal, a drain of the first NFET is connected to an array supply voltage, and a gate of the first NFET is connected to a first attenuation signal, and

wherein a source of the second NFET is connected to the control signal, a drain of the second NFET is connected to the array supply voltage, and a gate of the second NFET is connected to a second attenuation signal.

2. The device of claim 1, wherein the clamping device further comprises an inverter, and a third NFET connected to the control signal.

3. The device of claim 2, wherein a source of the third NFET is connected to the control signal, a drain of the third NFET is connected to the array supply voltage, and a gate of the third NFET is connected to a third attenuation signal.

4. The device of claim 3, wherein the first attenuation signal, the second attenuation signal, and the third attenuation signal are generated from a logic structure comprising three OR gates, and are configured to individually activate either the first NFET, the second NFET, or the third NFET such that only one of the first NFET, the second NFET, and the third NFET modify the control signal as a function of the supply voltage and the process to attenuate the amount of the boost.

5. The device of claim 4, wherein a width of the channel of each of the first NFET, the second NFET, and the third NFET is different such that each of the first NFET, the second NFET, and the third NFET modifies the control signal in a different manner.

6. The device of claim 2, wherein each of the first NFET, the second NFET, and the third NFET is connected to a first attenuation signal, a second attenuation signal, and a third attenuation signal, respectively.

7. The device of claim 6, wherein the first attenuation signal, the second attenuation signal, and the third attenuation signal are generated from a logic structure, and are configured to individual activate either the first NFET, the second NFET, or the third NFET such that only one of the first NFET, the second NFET, and the third NFET modify the control signal as a function of the supply voltage and the process to attenuate the amount of the boost.

8. The device of claim 7, wherein a width of a channel of each of the first NFET, the second NFET, and the third NFET is different such that each of the first NFET, the second NFET, and the third NFET modifies the control signal in a different manner.

9. The device of claim 8, wherein the width of the channel of the second NFET is less than the width of the channel of the first NFET, and the width of the channel of the first NFET is less than the width of the channel of the third NFET.

10. The device of claim 7, wherein the logic structure comprises an OR gate configured to generate a pulsed signal on the first attenuation signal, the second attenuation signal, and the third attenuation signal to allow for clamping of a signal until and during the boost and allow for the signal to proceed to the ground after the boost.

11. A static random access memory (SRAM) write assist attenuation circuit, comprising:

a clamping device comprising a first NFET, a second NFET, and a third NFET connected to a control signal; and

a logic structure comprising one or more OR gates configured to generate a first attenuation signal, a second attenuation signal, and a third attenuation signal,

wherein the first attenuation signal, the second attenuation signal, and the third attenuation signal are configured to individually activate either the first NFET, the second NFET, or the third NFET such that only one of the first NFET, the second NFET, and the third NFET modify the control signal as a function of a supply voltage and a process to attenuate an amount of boost applied to pull one of a plurality of true bit lines or one of a plurality of complement bit lines below ground in an active phase of a write cycle.

12. The SRAM write assist attenuation circuit of claim 11, wherein one of the one or more OR gates is configured to generate a pulsed signal on the first attenuation signal, the second attenuation signal, and the third attenuation signal to allow for clamping of a signal until and during the boost and allow for the signal to proceed to the ground after the boost.

13. The SRAM write assist attenuation circuit of claim 11, wherein:

a source of the first NFET is connected to the control signal, a drain of the first NFET is connected to a voltage control signal, and a gate of the first NFET is connected to the first attenuation signal;

a source of the second NFET is connected to the control signal, a drain of the second NFET is connected to the voltage control signal, and a gate of the second NFET is connected to the second attenuation signal; and

a source of the third NFET is connected to the control signal, a drain of the third NFET is connected to the voltage control signal, and a gate of the third NFET is connected to the third attenuation signal.

14. The SRAM write assist attenuation circuit of claim 11, wherein a width of a channel of each of the first NFET, the second NFET, and the third NFET is different such that each of the first NFET, the second NFET, and the third NFET modifies the control signal in a different manner.

15. A static random access memory (SRAM) device, comprising:

a memory array comprising a plurality of SRAM cells;

a plurality of true bit lines each connected to a column of the memory array;

a plurality of complement bit lines each forming a differential pair with, and in a same column as, one of the plurality of true bit lines;

a write driver connected to each of the differential pair of bit lines in each of the plurality of SRAM cells of the memory array; and

a write assist attenuation circuit connected to the write driver, the write assist attenuation circuit comprising;

a clamping device comprising a first NFET, a second NFET, and a third NFET connected to a control signal; and

a logic structure configured to generate a first attenuation signal, a second attenuation signal, and a third attenuation signal,

wherein the first attenuation signal, the second attenuation signal, and the third attenuation signal are configured to individually activate either the first NFET, the second NFET, or the third NFET such that only one of the first NFET, the second NFET, and the third NFET modify the control signal as a function of a supply voltage and a process to attenuate an amount of boost applied to pull one of the plurality of true bit lines or one of the plurality of complement bit lines below ground in an active phase of a write cycle.

16. The SRAM device of claim 15, wherein the logic structure comprises an OR gate configured to generate a pulsed signal on the first attenuation signal, the second attenuation signal, and the third attenuation signal to allow for clamping of a n-channel metal-oxide-semiconductor field-effect transistor disable (NDIS) signal until and during the boost and allow for the NDIS signal to proceed to the ground after the boost.

17. The SRAM device of claim 15, wherein a width of a channel of each of the first NFET, the second NFET, and the third NFET is different such that each of the first NFET, the second NFET, and the third NFET modifies the control signal in a different manner.