Method and apparatus for faster determination of a cell state of a resistive memory cell using a parallel resistor

• US 9,496,031 B2
• Filed: 06/17/2015
• Issued: 11/15/2016
• Est. Priority Date: 03/26/2014
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Papandreou, Nikolaos, Pozidis, Charalampos, Sebastian, Abu, Stanisavljevic, Milos
• Primary Examiner(s): Dinh, Son
• Assistant Examiner(s): Begum, Sultana
• Application Number:
  US14/742,363
• Publication Number:
  US 20150287456A1
• Time in Patent Office: 517 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: G11C 11/5678 using amorphous/crystalline phase transition storage elements
• CPC Class Codes: G11C 13/0004 comprising amorphous/crystalline phase transition cells
• CPC Class Codes: G11C 13/004 Reading or sensing circuits or methods
• CPC Class Codes: G11C 13/0069 Writing or programming circuits or methods
• CPC Class Codes: G11C 2013/0057 Read done in two steps, e.g. wherein the cell is read twice and one of the two read values serving as a reference value
• CPC Class Codes: G11C 2213/79 Array wherein the access device being a transistor

Abstract

A device for determining an actual cell state of a resistive memory cell having a plurality M of programmable cell states comprising a sensing circuit, a settling circuit, a prebiasing circuit, and a resistor coupled in parallel to the resistive memory cell, wherein the resistor is configured to reduce an effective resistance seen by the prebiasing circuit. The sensing circuit is configured to sense a sensing voltage of the resistive memory cell and output a resultant value in response to the sensing voltage which is indicative for the actual cell state. The settling circuit is configured to settle the sensing voltage to a certain target voltage representing one of the M programmable cell states. The prebiasing circuit is configured to prebiase a bitline capacitance of the resistive memory cell such the sensing voltage is close to the certain target voltage.

Claims

1. A method for determining an actual cell state of a resistive memory cell having a plurality of programmable cell states, the method comprising:

providing a prebiasing circuit;

coupling a resistor in parallel to the resistive memory cell such that the resistor is configured to reduce an effective resistance seen by the prebiasing circuit;

prebiasing a bitline capacitance of the resistive memory cell by the prebiasing circuit such that a sensing voltage of the resistive memory cell is close to a certain target voltage which is indicative of the actual cell state;

settling the sensing voltage to the certain target voltage;

sensing the sensing voltage of the resistive memory cell; and

outputting a resultant value in response to the sensing voltage.

2. The method of claim 1, wherein a resistance of the resistor is at least five times smaller than a highest resistance value of the resistive memory cell.

3. The method of claim 1, wherein a resistance of the resistor is between five and fifteen times smaller than a highest resistance value of the resistive memory cell.

4. The method of claim 1, wherein the prebiasing circuit is coupled to a first node connected to a bitline of the resistive memory cell and to the resistor.

5. The method of claim 4, further comprising controlling a number of switches such that, during the prebiasing, the prebiasing circuit is connected to the first node and, during the settling, a settling circuit is connected to the first node and the prebiasing circuit is disconnected from the first node.

6. The method of claim 5, further comprising comparing a first current flowing through the resistive memory cell and the resistor coupled in parallel to the resistive memory cell and a second current provided by a current mirror of the settling circuit to provide a comparison result.

7. The method of claim 6, further comprising controlling the number of switches such that the prebiasing circuit is connected to the first node when the comparison result indicates that the first current is smaller than the second current and such that the settling circuit is connected to the first node and the prebiasing circuit is disconnected from the first node when the comparison result indicates that the first current is greater than or equal to the second current.

8. The method of claim 7, further comprising feeding, during the prebiasing, a number of gradual rising biasing voltages to the prebiasing circuit.

9. The method of claim 8, wherein the number of gradual rising biasing voltages includes a minimum biasing voltage corresponding to a maximum voltage allowed for the cell state having a lowest resistance value when the resistive memory cell is in a set state, a maximum biasing voltage corresponding to a maximum sensing voltage when the resistive memory cell is in a reset state, and gradual voltage steps between the minimum biasing voltage and the maximum biasing voltage.

10. The method of claim 6, wherein comparing the first current and the second current includes comparing an output voltage provided by the current mirror of the settling circuit and a reference voltage to provide the comparison result.