Dynamically optimizing flash data retention or endurance based on data write frequency
First Claim
1. A method in a data storage system including a non-volatile memory array controlled by a controller, the method comprising:
- during an operating lifetime of the non-volatile memory array, the controller determining a write frequency of a logical address that has been mapped, in turn, to a plurality of different physical subsets of the non-volatile memory array including a current physical subset to which the logical address is mapped; and
based on the determined write frequency of the logical address, the controller dynamically adjusting at least one operating parameter of a program/erase (P/E) cycle to optimize at least one of endurance of the current physical subset and data retention time of the current physical subset of the non-volatile memory array, wherein the at least one operating parameter includes at least one of a set including a pulse budget, a verify voltage and a verify threshold.
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Abstract
In a data storage system including a non-volatile memory array, a controller determines a write frequency of a logical address mapped to a physical subset of the non-volatile memory array. Based on the determined write frequency of the logical address, the controller dynamically adjusts at least one operating parameter of a program/erase (P/E) cycle to optimize at least one of endurance of the block and data retention time of the physical subset of the non-volatile memory array. The at least one operating parameter includes one or more of a set including a pulse budget, a verify voltage and a verify threshold.
52 Citations
20 Claims
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1. A method in a data storage system including a non-volatile memory array controlled by a controller, the method comprising:
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during an operating lifetime of the non-volatile memory array, the controller determining a write frequency of a logical address that has been mapped, in turn, to a plurality of different physical subsets of the non-volatile memory array including a current physical subset to which the logical address is mapped; and based on the determined write frequency of the logical address, the controller dynamically adjusting at least one operating parameter of a program/erase (P/E) cycle to optimize at least one of endurance of the current physical subset and data retention time of the current physical subset of the non-volatile memory array, wherein the at least one operating parameter includes at least one of a set including a pulse budget, a verify voltage and a verify threshold. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A data storage system, comprising:
a controller configured to be coupled to a non-volatile memory array, wherein the controller, during an operating lifetime of the non-volatile memory array, determines a write frequency of a logical address that has been mapped, in turn, to a plurality of different physical subsets of the non-volatile memory array including a current physical subset to which the logical address is mapped, and based on the determined write frequency of the logical address, dynamically adjusts at least one operating parameter of a program/erase (P/E) cycle to optimize at least one of endurance of the current physical subset and data retention time of the current physical subset of the non-volatile memory array, wherein the at least one operating parameter includes at least one of a set including a pulse budget, a verify voltage and a verify threshold. - View Dependent Claims (9, 10, 11, 12, 13, 14, 15)
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16. A program product, comprising:
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a storage device; and program code stored in the storage device, wherein the program code, when executed by a controller that controls a non-volatile memory array of a data storage system, causes the controller to perform; during an operating lifetime of the non-volatile memory array, the controller determining a write frequency of a logical address that has been mapped, in turn, to a plurality of different physical subsets of the non-volatile memory array including a current physical subset to which the logical address is mapped; and based on the determined write frequency of the logical address, the controller dynamically adjusting at least one operating parameter of a program/erase (P/E) cycle to optimize at least one of endurance of the current physical subset and data retention time of the current physical subset of the non-volatile memory array, wherein the at least one operating parameter includes at least one of a set including a pulse budget, a verify voltage and a verify threshold. - View Dependent Claims (17, 18, 19, 20)
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Specification