Dynamically optimizing flash data retention or endurance based on data write frequency

• US 9,496,043 B1
• Filed: 06/24/2015
• Issued: 11/15/2016
• Est. Priority Date: 06/24/2015
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Camp, Charles J., Fisher, Timothy J., Fry, Aaron D., Papandreou, Nikolaos, Parnell, Thomas, Pozidis, Charalampos, Walls, Andrew D.
• Primary Examiner(s): Auduong, Gene
• Application Number:
  US14/749,206
• Time in Patent Office: 510 Days
• Field of Search: 365/185.11, 365/185.17, 365/185.19, 365/185.23, 365/185.24, 365/185.29, 365/185.33
• US Class Current: 1/1
• CPC Class Codes: G06F 2212/1036 Life time enhancement
• CPC Class Codes: G11C 16/16 for erasing blocks, e.g. arrays, words, groups
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/3459 Circuits or methods to verify correct programming of nonvolatile memory cells
• CPC Class Codes: G11C 16/349 Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles

Abstract

In a data storage system including a non-volatile memory array, a controller determines a write frequency of a logical address mapped to a physical subset of the non-volatile memory array. Based on the determined write frequency of the logical address, the controller dynamically adjusts at least one operating parameter of a program/erase (P/E) cycle to optimize at least one of endurance of the block and data retention time of the physical subset of the non-volatile memory array. The at least one operating parameter includes one or more of a set including a pulse budget, a verify voltage and a verify threshold.

Claims

1. A method in a data storage system including a non-volatile memory array controlled by a controller, the method comprising:

during an operating lifetime of the non-volatile memory array, the controller determining a write frequency of a logical address that has been mapped, in turn, to a plurality of different physical subsets of the non-volatile memory array including a current physical subset to which the logical address is mapped; and

based on the determined write frequency of the logical address, the controller dynamically adjusting at least one operating parameter of a program/erase (P/E) cycle to optimize at least one of endurance of the current physical subset and data retention time of the current physical subset of the non-volatile memory array, wherein the at least one operating parameter includes at least one of a set including a pulse budget, a verify voltage and a verify threshold.

2. The method of claim 1, wherein:

the non-volatile memory array includes multiple blocks of memory; and

the controller performs the dynamically adjusting the at least one operating parameter on a per-block basis.

3. The method of claim 1, wherein the pulse budget, verify voltage and verify threshold are operating parameters of a program operation.

4. The method of claim 1, wherein the pulse budget, verify voltage and verify threshold are operating parameters of an erase operation.

5. The method of claim 1, wherein the dynamically adjusting the at least one operating parameter further includes dynamically adjusting the at least one operating parameter based on a health metric related to a bit error rate of the current physical subset of the non-volatile memory array.

6. The method of claim 1, wherein the dynamically adjusting includes dynamically adjusting the at least one operating parameter such that a bit error rate of the current physical subset is maintained below a bit error rate threshold for at least a predetermined number of P/E cycles.

7. The method of claim 1, wherein the dynamically adjusting includes dynamically adjusting the at least one operating parameter such that a data retention time of the current physical subset is maintained above a threshold data retention time for at least a predetermined number of P/E cycles.

8. A data storage system, comprising:

a controller configured to be coupled to a non-volatile memory array, wherein the controller, during an operating lifetime of the non-volatile memory array, determines a write frequency of a logical address that has been mapped, in turn, to a plurality of different physical subsets of the non-volatile memory array including a current physical subset to which the logical address is mapped, and based on the determined write frequency of the logical address, dynamically adjusts at least one operating parameter of a program/erase (P/E) cycle to optimize at least one of endurance of the current physical subset and data retention time of the current physical subset of the non-volatile memory array, wherein the at least one operating parameter includes at least one of a set including a pulse budget, a verify voltage and a verify threshold.

9. The data storage system of claim 8, wherein:

the non-volatile memory array includes multiple blocks of memory; and

the controller dynamically adjusts the at least one operating parameter on a per-block basis.

10. The data storage system of claim 8, wherein the pulse budget, verify voltage and verify threshold are operating parameters of a program operation.

11. The data storage system of claim 8, wherein the pulse budget, verify voltage and verify threshold are operating parameters of an erase operation.

12. The data storage system of claim 8, wherein the controller dynamically adjusts the at least one operating parameter based on a health metric related to a bit error rate of the current physical subset of the non-volatile memory array.

13. The data storage system of claim 8, wherein the controller dynamically adjusts the at least one operating parameter such that a bit error rate of the current physical subset is maintained below a bit error rate threshold for at least a predetermined number of P/E cycles.

14. The data storage system of claim 8, wherein the controller dynamically adjusts the at least one operating parameter such that a data retention time of the current physical subset is maintained above a threshold data retention time for at least a predetermined number of P/E cycles.

15. The data storage system of claim 8, and further comprising the non-volatile memory array coupled to the controller.

16. A program product, comprising:

a storage device; and

program code stored in the storage device, wherein the program code, when executed by a controller that controls a non-volatile memory array of a data storage system, causes the controller to perform;

during an operating lifetime of the non-volatile memory array, the controller determining a write frequency of a logical address that has been mapped, in turn, to a plurality of different physical subsets of the non-volatile memory array including a current physical subset to which the logical address is mapped; and

based on the determined write frequency of the logical address, the controller dynamically adjusting at least one operating parameter of a program/erase (P/E) cycle to optimize at least one of endurance of the current physical subset and data retention time of the current physical subset of the non-volatile memory array, wherein the at least one operating parameter includes at least one of a set including a pulse budget, a verify voltage and a verify threshold.

17. The program product of claim 16, wherein the pulse budget, verify voltage and verify threshold are operating parameters of a program operation.

18. The program product of claim 16, wherein the pulse budget, verify voltage and verify threshold are operating parameters of an erase operation.

19. The program product of claim 16, wherein the program code causes the controller to dynamically adjust the at least one operating parameter such that a bit error rate of the current physical subset is maintained below a bit error rate threshold for at least a predetermined number of P/E cycles.

20. The program product of claim 16, wherein the program code causes the controller to dynamically adjust the at least one operating parameter such that a data retention time of the current physical subset is maintained above a threshold data retention time for at least a predetermined number of P/E cycles.