Memory cell and memory
First Claim
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1. A memory cell comprising:
- a Static Random Access Memory (SRAM) cell comprising a reset-set (RS) flip-flop; and
a Read Only Memory (ROM) cell connected to the RS flip-flop of the SRAM cell to set logic states of internal latch nodes of the RS flip-flop when the ROM cell is triggered, the ROM cell comprising a transistor that couples one of the internal latch nodes of the RS flip-flop with ground and a gate of that is used to receive a triggering signal from a triggering word line.
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Abstract
In various embodiments, a memory cell and a memory are provided. The memory cell comprises a Static Random Access Memory (SRAM) cell including a reset-set (RS) flip-flop and a Read Only Memory (ROM) cell being connected (or coupled) to the SRAM cell to set logic states of internal latch nodes of the RS flip-flop when the ROM cell is triggered. The size of the memory cells proposed in an embodiment of the invention is much smaller than the sum of the size of ROM cells and the size of SRAM cells with the capacity of the memory cells same as the sum of the capacity of the ROM cells and the capacity of the SRAM cells.
80 Citations
20 Claims
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1. A memory cell comprising:
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a Static Random Access Memory (SRAM) cell comprising a reset-set (RS) flip-flop; and a Read Only Memory (ROM) cell connected to the RS flip-flop of the SRAM cell to set logic states of internal latch nodes of the RS flip-flop when the ROM cell is triggered, the ROM cell comprising a transistor that couples one of the internal latch nodes of the RS flip-flop with ground and a gate of that is used to receive a triggering signal from a triggering word line. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A memory array comprising:
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multiple memory cells, each memory cell comprising; a Static Random Access Memory (SRAM) cell comprising a reset-set (RS) flip-flop; and a Read Only Memory (ROM) cell coupled to the SRAM cell to set logic states of internal latch nodes of the RS flip-flop when the ROM cell is triggered; multiple bit lines, each bit line coupled to memory cells in a respective column; multiple word lines, each word line coupled to memory cells in a respective row; and multiple triggering word lines, each triggering word line coupled to memory cells in a respective row to trigger the ROM cells of the memory cells in the respective row. - View Dependent Claims (10, 11, 12, 13, 14, 15, 16)
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17. A memory cell comprising:
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a Static Random Access Memory (SRAM) cell comprising a reset-set (RS) flip-flop; and a Read Only Memory (ROM) cell connected to the RS flip-flop of the SRAM cell to set logic states of internal latch nodes of the RS flip-flop when the ROM cell is triggered, the ROM cell comprising; a first transistor that couples a first internal latch node of the RS flip-flop with ground and a gate that is used to receive a triggering signal from a triggering word line; and a second transistor, wherein its source is coupled to the ground and its drain is decoupled from a second internal latch node of the RS flip-flop, and its gate is used to receive the triggering signal from the triggering word line. - View Dependent Claims (18, 19, 20)
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Specification