Memory device comprising electrically floating body transistor
First Claim
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1. A semiconductor memory instance comprising:
- an array of memory cells, the array comprising;
a plurality of semiconductor memory cells arranged in at least one column and at least one row, each said semiconductor memory cell comprising;
a floating body region configured to be charged to a level indicative of a state of the memory cell;
a plurality of buried well regions contacting said floating body regions of said plurality of semiconductor cells, wherein each of said buried well regions is configured to be individually selected;
a first decoder circuit to select at least one of said at least one column or at least one of said at least one row; and
a second decoder circuit to select at least one of said buried well regions.
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Abstract
A semiconductor memory instance is provided that includes an array of memory cells. The array includes a plurality of semiconductor memory cells arranged in at least one column and at least one row. Each of the semiconductor memory cells includes a floating body region configured to be charged to a level indicative of a state of the memory cell. Further includes are a plurality of buried well regions, wherein each of the buried well regions can be individually selected, and a decoder circuit to select at least one of the buried well regions.
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20 Claims
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1. A semiconductor memory instance comprising:
an array of memory cells, the array comprising; a plurality of semiconductor memory cells arranged in at least one column and at least one row, each said semiconductor memory cell comprising;
a floating body region configured to be charged to a level indicative of a state of the memory cell;a plurality of buried well regions contacting said floating body regions of said plurality of semiconductor cells, wherein each of said buried well regions is configured to be individually selected; a first decoder circuit to select at least one of said at least one column or at least one of said at least one row; and a second decoder circuit to select at least one of said buried well regions. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A semiconductor memory instance comprising:
an array of semiconductor memory cells, the array comprising at least two memory sub-arrays, each memory sub-array comprising; a plurality of said semiconductor memory cells arranged in at least one column and at least one row, each said semiconductor memory cell comprising;
a floating body region configured to be charged to a level indicative of a state of said semiconductor memory cell;a buried well region in contact with said floating body regions of said plurality of memory cells in one of said memory sub-arrays; and a buried well decoder circuit electrically connected to said buried well region to select said buried well region, wherein said buried well decoder circuit is configured to select said buried well region independently of other inputs to said semiconductor memory cells. - View Dependent Claims (11, 12, 13)
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14. An integrated circuit device comprising:
an array of semiconductor memory cells, the array comprising; a plurality of said semiconductor memory cells arranged in at least one column and at least one row, each said semiconductor memory cell comprising;
a floating body region configured to be charged to a level indicative of a state of said semiconductor memory cell, respectively;a plurality of buried well regions in contact with said floating body regions of said plurality of semiconductor memory cells, wherein each said buried well region is configured to be individually selected; and a buried well decoder circuit electrically connected to said buried well regions to select at least one of said buried well regions, wherein said buried well decoder circuit is configured to select said at least one buried well region independently of other inputs to said semiconductor memory cells. - View Dependent Claims (15, 16, 17, 18, 19, 20)
Specification