Stacked semiconductor devices and methods of forming same

• US 9,496,189 B2
• Filed: 10/17/2014
• Issued: 11/15/2016
• Est. Priority Date: 06/13/2014
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Yu, Chen-Hua, Lee, Chien-Hsun, Wang, Tsung-Ding, Cheng, Jung Wei
• Primary Examiner(s): WHALEN, DANIEL B
• Application Number:
  US14/517,627
• Publication Number:
  US 20150364386A1
• Time in Patent Office: 760 Days
• US Class Current: 1/1
• CPC Class Codes: H01L 22/14 for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
• CPC Class Codes: H01L 22/20 Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
• CPC Class Codes: H01L 22/32 Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors arrangements for conducting electric current to or from the solid state body in operation H01L23/48
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/17181 On opposite sides of the body
• CPC Class Codes: H01L 2224/214 Connecting portions
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/73267 Layer and HDI connectors
• CPC Class Codes: H01L 2224/81 using a bump connector
• CPC Class Codes: H01L 2224/83 using a layer connector
• CPC Class Codes: H01L 2224/92224 the second connecting process involving a build-up interconnect
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2225/06596 Structural arrangements for testing
• CPC Class Codes: H01L 24/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence

Abstract

Stacked semiconductor devices and methods of forming the same are disclosed. First tier workpieces are mounted on a top surface of a semiconductor device to form first tier stacks, the semiconductor device comprising one or more integrated circuit dies, the semiconductor device having one or more test pads per integrated circuit die on the top surface of the semiconductor device. Each of the first tier stacks is electrically tested to identify first known good stacks and first known bad stacks. Second tier workpieces are mounted atop the first known good stacks, thereby forming second tier stacks. Each of the second tier stacks is electrically tested to identify second known good stacks and second known bad stacks. Stacking process further comprises one or more workpiece mounting/testing cycles. The stacking process continues until the stacked semiconductor devices comprise desired number of workpieces.

Claims

1. A method comprising:

forming a semiconductor device, the semiconductor device comprising integrated circuit dies, the semiconductor device having at least one test pad per integrated circuit die on a first side of the semiconductor device and having at least one external connector per integrated circuit die disposed on the first side of the semiconductor device;

mounting first tier workpieces on the first side of the semiconductor device, thereby forming first tier stacks, wherein the first tier workpieces are electrically coupled to corresponding integrated circuit dies, wherein the at least one test pad per integrated circuit die is interposed between a respective first tier workpiece on the integrated circuit die and the respective at least one external connector on the integrated circuit die; and

testing each of the first tier stacks and identifying first known good stacks and first known bad stacks.

2. The method of claim 1, wherein at least one of the first tier workpieces comprises an integrated circuit die.

3. The method of claim 1, wherein at least one of the first tier workpieces comprises an interposer.

4. The method of claim 1, further comprising mounting dummy workpieces atop the first known bad stacks.

5. The method of claim 1, wherein testing each of the first tier stacks comprises using the at least one test pad to test functionality of each of the first tier stacks.

6. The method of claim 1, further comprising:

mounting second tier workpieces atop the first known good stacks, thereby forming second tier stacks; and

testing each of the second tier stacks and identifying second known good stacks and second known bad stacks.

7. The method of claim 6, further comprising mounting dummy workpieces atop the second known bad stacks.

8. A method comprising:

forming a semiconductor device, the semiconductor device comprising;

integrated circuit dies;

at least one first connector and at least one second connector per integrated circuit die on a first side of the semiconductor device, the at least one first connector and the at least one second connector being electrically coupled to a corresponding integrated circuit die; and

at least one test pad per integrated circuit die on the first side of the semiconductor device, the at least one test pad being electrically coupled to the corresponding integrated circuit die;

mounting first tier workpieces on the first side of the semiconductor device using the at least one first connector, thereby forming first tier stacks;

testing each of the first tier stacks using the at least one test pad to identify first known good stacks and first known bad stacks; and

mounting dummy workpieces atop the first known bad stacks.

9. The method of claim 8, wherein at least one of the first tier workpieces comprises an integrated circuit die.

10. The method of claim 8, wherein at least one of the first tier workpieces comprises an interposer.

11. The method of claim 8, wherein the at least one test pad is interposed between the at least one first connector and the at least one second connector.

12. The method of claim 8, wherein the at least one test pad and the at least one first connector are formed by a same process.

13. The method of claim 8, further comprising:

mounting second tier workpieces atop the first known good stacks, thereby forming second tier stacks; and

testing each of the second tier stacks using the at least one test pad to identify second known good stacks and second known bad stacks.

14. A method comprising:

attaching a plurality of integrated circuit dies to a carrier;

forming a molding compound over the carrier and around each of the plurality of integrated circuit dies;

forming one or more redistribution layers (RDLs) over the molding compound and the plurality of integrated circuit dies;

forming a plurality of first connectors over the one or more RDLs;

forming a plurality of second connectors over the one or more RDLs, wherein a size of the plurality of first connectors is different from a size of the plurality of second connectors;

forming a plurality of test pads over the one or more RDLs, wherein the one or more RDLs electrically couple the plurality of first connectors, the plurality of second connectors and the plurality of test pads to the plurality of integrated circuit dies;

bonding first tier workpieces to the one or more RDLs using the plurality of first connectors, thereby forming first tier stacks, wherein each of the first tier stacks comprises one of the plurality of integrated circuit dies and one of the first tier workpieces; and

testing the first tier stacks using the plurality of testing pads to identify first known good stacks and first known bad stacks.

15. The method of claim 14, further comprising mounting dummy workpieces atop the first known bad stacks.

16. The method of claim 14, further comprising:

mounting second tier workpieces atop the first known good stacks, thereby forming second tier stacks; and

testing the second tier stacks using the plurality of testing pads to identify second known good stacks and second known bad stacks.

17. The method of claim 16, further comprising mounting dummy workpieces atop the first known bad stacks and the second known bad stacks.

18. The method of claim 14, wherein the plurality of first connectors and the plurality of test pads are formed using a same method.

19. The method of claim 14, wherein testing the first tier stacks comprises performing electronic functional testing on the first tier stacks.