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Interposer for integrated circuit chip package

  • US 9,496,248 B2
  • Filed: 01/06/2014
  • Issued: 11/15/2016
  • Est. Priority Date: 01/06/2014
  • Status: Active Grant
First Claim
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1. An interposer for an electronic circuit chip package, the interposer comprising:

  • a substrate having a first surface, a second surface substantially parallel to and opposite the first surface, a third surface substantially parallel to the first surface and the second surface, and an orthogonal surface that is substantially orthogonal to and intersects the first surface and the third surface;

    a recess formed in the substrate and defined by the third surface and the orthogonal surface;

    a first plurality of conductive vias that pass from the second surface to the first surface; and

    a second plurality of conductive vias that pass from the second surface to the third surface;

    wherein;

    the first plurality of conductive vias is configured to electrically couple a first chip mounted to the second surface to a package substrate coupled to the first surface;

    the second plurality of conductive vias is configured to electrically couple the first chip mounted to the second surface to a second chip mounted to the third surface within the recess;

    the first chip and the second chip are vertically displaced from each other but not laterally displaced from each other; and

    a resistance of the electronic circuit chip package to thermal heat transfer from the first chip through the interposer to the vertically displaced but not laterally displaced second chip is greater than 1000 millimeters squared Kelvin per watt.

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