Stacked CMOS chipset having an insulating layer and a secondary layer and method of forming same

• US 9,496,255 B2
• Filed: 01/24/2012
• Issued: 11/15/2016
• Est. Priority Date: 11/16/2011
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Zuo, Chengjie, Yun, Changhan, Park, Sang-June, Lo, Chi Shun, Velez, Mario F., Kim, Jonghae
• Primary Examiner(s): Campbell, Shaun
• Application Number:
  US13/356,717
• Publication Number:
  US 20130120951A1
• Time in Patent Office: 1,757 Days
• Field of Search: 438106-110, 438/113, 438/118, 257/686, 257/E21.505, 257/E21.506, 257/E25.013, 361/783
• US Class Current: 1/1
• CPC Class Codes: H01L 2224/18 High density interconnect [HDI] connectors; Manufacturing methods related thereto
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout

Abstract

A chipset includes a sheet of glass, quartz or sapphire and a first wafer having at least one first circuit layer on a first side of a first substrate layer. The first wafer is connected to the sheet such that the at least one first circuit layer is located between the first substrate layer and the sheet. A second wafer having at least one second circuit layer on a first side of a second substrate layer is connected to the first substrate layer such that the at least one second circuit layer is located between the second substrate layer and the first substrate layer. Also a method of forming a chipset.

Claims

1. An apparatus comprising:

a layer of glass, quartz or sapphire;

a first silicon-on-insulator (SOI) structure comprising a first insulating layer and at least one first circuit layer formed on a first side of the first insulating layer, the first SOI structure being bonded to the layer of glass, quartz or sapphire such that the at least one first circuit layer is located between the first insulating layer and the layer of glass, quartz or sapphire, wherein the first insulating layer comprises a second side opposite the first side of the first insulating layer;

an adhesive layer disposed between the layer of glass, quartz or sapphire and the first SOI structure such that the at least one first circuit layer of the first SOI structure is bonded directly to the layer of glass, quartz or sapphire using the adhesive layer; and

a second SOI structure comprising a second insulating layer and at least one second circuit layer, wherein the second insulating layer comprises a first side and a second side, the first side of the second insulating layer facing the second side of the first insulating layer and the second side of the second insulating layer is opposite the first side of the second insulating layer, wherein the at least one second circuit layer comprises at least one first passive circuit element formed on and in direct contact with the first side of the second insulating layer and at least one second passive circuit element formed on and in direct contact with the second side of the second insulating layer, the second SOI structure being bonded to the first insulating layer such that the at least one first passive circuit element is located between the second insulating layer and the first insulating layer, wherein the second side of the first insulating layer is bonded to the at least one second circuit layer.

2. The apparatus of claim 1, wherein the at least one first circuit layer comprises a plurality of CMOS transistors.

3. The apparatus of claim 1, wherein the at least one second passive circuit element comprises at least one microelectromechanical system (MEMS) element.

4. The apparatus of claim 1, wherein the at least one second passive circuit element comprises at least one sensor.

5. The apparatus of claim 1, further comprising a second adhesive layer disposed between the first SOI structure and the second SOI structure such that the second side of the first insulating layer is bonded directly to the at least one second circuit layer using the second adhesive layer.

6. The apparatus of claim 1 integrated into at least one semiconductor die.

7. The apparatus of claim 1 integrated into a device selected from the group consisting of a set top box, a music player, a video player, an entertainment unit, a navigation device, a communications device, a personal digital assistant (PDA), a fixed location data unit, and a computer.

8. The apparatus of claim 1,

wherein the at least one first circuit layer comprises a plurality of complementary metal oxide semiconductor (CMOS) transistors,

wherein the at least one second circuit layer comprises or supports at least one passive component or at least one MEMS element,

wherein the first SOI structure is bonded directly to the layer of glass, quartz or sapphire, and

wherein the second SOI structure is bonded directly to the first insulating layer.

9. The apparatus of claim 1, including a third SOI structure comprising SOI and having at least one third circuit layer on a first side of a third insulating layer, the third SOI structure being connected to the first SOI structure such that the at least one third circuit layer is located between the first insulating layer and the second insulating layer.

10. The apparatus of claim 9, wherein the at least one third circuit layer comprises CMOS transistors.

11. The apparatus of claim 9, wherein the second SOI structure is bonded directly to the third SOI structure such that the at least one second circuit layer is located between the second insulating layer and the third insulating layer.

12. The apparatus of claim 9, wherein the at least one first circuit layer includes a digital circuit and the at least one third circuit layer includes an analog circuit.

13. The apparatus of claim 9, wherein the at least one first circuit layer includes a digital circuit, the at least one second circuit layer includes or supports a passive device or a MEMS element and the at least one third circuit layer includes an analog or radio frequency (RF) circuit.

14. The apparatus of claim 9, wherein a surface area of the first insulating layer is substantially equal to a surface area of the second insulating layer, and the surface area of the second insulating layer is substantially equal to a surface area of the third insulating layer.

22. The apparatus of claim 1, wherein the at least one first circuit layer comprises a plurality of CMOS transistors and wherein the at least one second circuit layer comprises at least one high-Q passive element.

23. The apparatus of claim 1, wherein the at least one first circuit layer comprises a plurality of CMOS transistors and wherein the at least one second circuit layer comprises at least one semiconductor varactor.

24. The apparatus of claim 1, wherein the at least one first circuit layer comprises a plurality of CMOS transistors and wherein the at least one second circuit layer comprises at least one MEMS tunable capacitor.

25. The apparatus of claim 1, wherein the at least one first circuit layer comprises a plurality of CMOS transistors and wherein the at least one second circuit layer comprises at least one radio frequency (RF) switch.

15. An apparatus comprising:

means for supporting a first silicon-on-insulator (SOI) structure, wherein the first SOI structure comprises a first insulating layer means for insulating and at least one first circuit means for processing signals formed on a first side of the first insulating layer means, the first SOI structure being bonded to the means for supporting such that the at least one first circuit means is located between the first insulating layer means and the means for supporting, wherein the first insulating layer means comprises a second side opposite the first side of the first insulating layer means;

an adhesive layer disposed between the means for supporting and the first SOI structure such that the at least one first circuit means of the first SOI structure is bonded directly to the means for supporting using the adhesive layer; and

a second SOI structure comprising a second insulating layer means and at least one second circuit means for processing signals, wherein the second insulating layer means comprises a first side and a second side, the first side of the second insulating layer means facing the second side of the first insulating layer means and the second side of the second insulating layer means is opposite the first side of the second insulating layer means, wherein the at least one second circuit means comprises at least one first passive circuit element formed on and in direct contact with the first side of the second insulating layer means and at least one second passive circuit element formed on and in direct contact with the second side of the second insulating layer means, the second SOI structure being bonded to the first insulating layer means such that the at least one first passive circuit element is located between the second insulating layer means and the first insulating layer means, wherein the second side of the first insulating layer means is bonded to the at least one second circuit means.

16. The apparatus of claim 15, wherein the at least one first circuit means comprises a plurality of CMOS transistors.

17. The apparatus of claim 15, wherein the at least one second passive circuit element comprises at least one microelectromechanical system (MEMS) element or at least one sensor.

18. The apparatus of claim 15 integrated into at least one semiconductor die.

19. The apparatus of claim 15 integrated into a device selected from the group consisting of a set top box, a music player, a video player, an entertainment unit, a navigation device, a communications device, a personal digital assistant (PDA), a fixed location data unit, and a computer.

20. The apparatus of claim 15,

wherein the at least one first circuit means comprises a plurality of CMOS transistors,

wherein the at least one second circuit means comprises or supports at least one passive component or at least one MEMS element,

wherein the first SOI structure is bonded directly to the means for supporting, and

wherein the second SOI structure is bonded directly to the first insulating layer means.

21. The apparatus of claim 15, wherein the means for supporting comprises a layer of glass or a layer of quartz or a layer of sapphire.