3DIC system with a two stable state memory and back-bias region

• US 9,496,271 B2
• Filed: 10/03/2014
• Issued: 11/15/2016
• Est. Priority Date: 03/11/2013
• Status: Active Grant

• Current Assignee: Monolithic 3D, Inc.
• Original Assignee: Monolithic 3D, Inc.
• Inventors: Or-Bach, Zvi, Widjaja, Yuniarto
• Primary Examiner(s): Lam, David
• Application Number:
  US14/506,160
• Publication Number:
  US 20150054090A1
• Time in Patent Office: 774 Days
• Field of Search: 365/51, 365/63, 365/185.18, 365/72, 257/499, 257/E23.145, 257/774, 257/401
• US Class Current: 1/1
• CPC Class Codes: G11C 11/404 with one charge-transfer gate, e.g. MOS transistor, per cell
• CPC Class Codes: G11C 11/4097 Bit-line organisation, e.g. bit-line layout, folded bit lines
• CPC Class Codes: G11C 11/412 using field-effect transistors only
• CPC Class Codes: G11C 16/02 electrically programmable
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 2213/71 Three dimensional array
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 29/7841 with floating body, e.g. programmable transistors
• CPC Class Codes: H10B 10/12 comprising a MOSFET load element
• CPC Class Codes: H10B 12/20 DRAM devices comprising floating-body transistors, e.g. floating-body cells
• CPC Class Codes: H10B 43/20 characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 63/30 comprising selection components having three or more electrodes, e.g. transistors
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A 3D IC based system, including: a first layer including first transistors; a second layer overlying the first layer, the second layer includes a plurality of second transistors, where the second layer includes at least one through second layer via having a diameter of less than 400 nm, and where at least one of the plurality of second transistors forms a two stable state memory cell including a back-bias region.

Claims

1. A 3D IC based system, comprising:

a first layer comprising first transistors;

a second layer overlying said first layer, said second layer comprises a plurality of second transistors,

wherein said second layer comprises at least one through second layer via having a diameter of less than 400 nm, and

wherein at least one of said plurality of second transistors forms a two stable state memory cell comprising a back-bias region.

2. A 3D IC based system according to claim 1,

wherein said back-bias region is disposed to one side of a channel region of said second transistors.

3. A 3D IC based system according to claim 1,

wherein at least one of said second transistors comprise a side gate on one side and said back-bias region on the opposite side of a channel region.

4. A 3D IC based system according to claim 1,

wherein said back-bias region comprises polysilicon.

5. A 3D IC based system according to claim 1,

wherein at least one of said plurality of second transistors and one of said first transistors share a back-bias region.

6. A 3D IC based system according to claim 1,

wherein at least two of said plurality of second transistors are connected by a common doped mono-crystalline structure.

7. A 3D IC based system according to claim 1,

wherein a first portion of at least one of said first transistors is self-aligned to a second portion of at least one of said plurality of second transistors.

8. A 3D IC based system, comprising:

a first layer comprising first transistors;

a second layer overlying said first layer, said second layer comprises a plurality of second transistors,

wherein said second layer thickness is less than 400 nm, and

wherein at least one of said plurality of second transistors forms a two stable state memory cell comprising a back-bias region.

9. A 3D IC based system according to claim 8,

wherein said back-bias region is disposed to one side of a channel region of said second transistors.

10. A 3D IC based system according to claim 8,

wherein at least one of said second transistors comprise a side gate on one side and said back-bias region on the opposite side of a channel region.

11. A 3D IC based system according to claim 8,

wherein said back-bias region comprises polysilicon.

12. A 3D IC based system according to claim 8,

wherein at least one of said plurality of second transistors and one of said first transistors share a back-bias region.

13. A 3D IC based system according to claim 8,

wherein at least two of said plurality of second transistors are connected by a common doped mono-crystalline structure.

14. A 3D IC based system according to claim 8,

wherein a first portion of at least one of said first transistors is self-aligned to a second portion of at least one of said plurality of second transistors.

15. A 3D IC based system, comprising:

a first layer comprising first transistors;

a second layer overlying said first layer, said second layer comprises a plurality of second transistors,

wherein a first portion of at least one of said first transistors is self-aligned to a second portion of at least one of said plurality of second transistors, and

wherein at least one of said plurality of second transistors forms a two stable state memory cell comprising a back-bias region.

16. A 3D IC based system according to claim 15,

wherein said back-bias region is disposed to one side of said of a channel region of second transistors.

17. A 3D IC based system according to claim 15,

wherein at least one of said second transistors comprise a side gate on one side and said back-bias region on the opposite side of a channel region.

18. A 3D IC based system according to claim 15,

wherein said back-bias region comprises polysilicon.

19. A 3D IC based system according to claim 15,

wherein at least one of said plurality of second transistors and one of said first transistors share a back-bias region.

20. A 3D IC based system according to claim 15,

wherein at least two of said plurality of second transistors are connected by a common doped mono crystal structure.