Super junction semiconductor device and method for manufacturing the same

• US 9,496,335 B2
• Filed: 10/14/2015
• Issued: 11/15/2016
• Est. Priority Date: 09/17/2013
• Status: Active Grant

• Current Assignee: Magnachip Semiconductor Limited (Magnachip Semiconductor)
• Original Assignee: Magnachip Semiconductor Limited (Magnachip Semiconductor)
• Inventors: Jun, Kwang Yeon, Choi, Chang Yong, Woo, Hyuk, Cho, Moon Soo, Kwon, Soon Tak
• Primary Examiner(s): Pham, Long
• Application Number:
  US14/882,606
• Publication Number:
  US 20160035825A1
• Time in Patent Office: 398 Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/265 producing ion implantation
• CPC Class Codes: H01L 21/26513 of electrically active species
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/66712 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors

Abstract

There is provided a super junction semiconductor device and a method of manufacturing the same. A super junction semiconductor device includes an n-type semiconductor region disposed in a substrate, two or more p-type semiconductor regions disposed adjacent to the n-type semiconductor region alternately in a direction parallel to a surface of the substrate, a p-type body region disposed on at least one of the p-type semiconductor regions, and a source region disposed in the p-type body region, and an n-type ion implantation region is formed along a lower end of the n-type semiconductor region and lower ends of the p-type semiconductor regions.

Claims

1. A method of forming a super junction semiconductor device, the method comprising:

forming a first epitaxial layer of first conductivity type above a substrate;

forming first pillar regions of second conductivity type by doping two or more areas of the first epitaxial layer with a second conductivity type dopant; and

forming an ion implantation region by doping the first pillar regions and the first epitaxial layer with a first conductivity type dopant; and

forming a second epitaxial layer and second pillar regions above the first epitaxial layer and the first pillar regions.

2. The method of claim 1, wherein one or more additional epitaxial layer and additional pillar regions are formed above the second epitaxial layer and the second pillar regions, such that the first pillar regions, the second pillar regions and the one or more additional pillar regions are aligned to form two or more second conductivity type pillar structures adjacent to a first conductivity type pillar structure,

the method further comprising forming a body region and source region above the two or more second conductivity type pillar structures.

3. The method of claim 2, further comprising:

forming a source electrode on the body region and the source region;

forming a gate electrode between the two or more second conductivity type pillar structures; and

forming a drain electrode below the substrate.

4. The method of claim 2, wherein a lower end of the second conductivity type pillar structures has a smaller width than an upper end of the second conductivity type pillar structures.

5. The method of claim 4, wherein the lower end of the second conductivity type pillar structures corresponds to a junction field effect (JFET) ion implantation region in which counter-doping is performed.

6. The method of claim 4, wherein counter-doping is not performed on the second pillar regions and the additional pillar regions formed above the second pillar regions.

7. The method of claim 1, wherein a dopant concentration of the first epitaxial layer between the two or more first pillar regions is higher than a net dopant concentration of the two or more first pillar regions after forming the JFET region.