Semiconductor device

• US 9,496,393 B2
• Filed: 01/14/2016
• Issued: 11/15/2016
• Est. Priority Date: 09/07/2009
• Status: Active Grant

• Current Assignee: ROHM Co., Ltd.
• Original Assignee: ROHM Co., Ltd.
• Inventors: Mitani, Shuhei, Nakano, Yuki, Watanabe, Heiji, Shimura, Takayoshi, Hosoi, Takuji, Kirino, Takashi
• Primary Examiner(s): Lee, Kyoung
• Application Number:
  US14/995,454
• Publication Number:
  US 20160133743A1
• Time in Patent Office: 306 Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/02164 the material being a silicon oxide, e.g. SiO2
• CPC Class Codes: H01L 21/02178 the material containing aluminium, e.g. Al2O3
• CPC Class Codes: H01L 21/0223 formation by oxidation, e.g. oxidation of the substrate
• CPC Class Codes: H01L 21/02236 group IV semiconductor
• CPC Class Codes: H01L 21/02247 formation by nitridation, e.g. nitridation of the substrate
• CPC Class Codes: H01L 21/02252 formation by plasma treatment, e.g. plasma oxidation of the substrate after treatment of an insulating film by plasma H01L21/3105 and subgroups
• CPC Class Codes: H01L 21/02255 formation by thermal treatment H01L21/02252 takes precedence; after treatment of an insulating film H01L21/3105 and subgroups
• CPC Class Codes: H01L 21/0445 the devices having semiconductor bodies comprising crystalline silicon carbide multistep processes for the manufacture of said devices H01L29/66053
• CPC Class Codes: H01L 21/049 Conductor-insulator-semiconductor electrodes, e.g. MIS contacts
• CPC Class Codes: H01L 21/8213 the substrate being a semiconductor, using SiC technology H01L21/8258 takes precedence
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/086 Impurity concentration or distribution
• CPC Class Codes: H01L 29/0869 Shape cell layout H01L29/0696
• CPC Class Codes: H01L 29/1087 characterised by the contact structure of the substrate region, e.g. for controlling or preventing bipolar effect
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/42356 Disposition, e.g. buried gate electrode H01L29/42324 and H01L29/4234 take precedence
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/45 Ohmic electrodes
• CPC Class Codes: H01L 29/511 : with a compositional variation, e.g. multilayer structures H01L29/516 takes precedence
• CPC Class Codes: H01L 29/513 : the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/518 : the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
• CPC Class Codes: H01L 29/66068 : the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
• CPC Class Codes: H01L 29/78 : with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 29/7802 : Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7813 : with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7827 : Vertical transistors H01L29/7802, H01L29/78642 take precedence

Abstract

A semiconductor device includes a semiconductor layer made of first conductivity type semiconductor layer; a second conductivity type well region formed on the semiconductor layer and having a channel region; a first conductivity type source region formed on the well region and including a first region adjacent to the well region and a second region adjacent to the first region; a gate insulating film formed on the semiconductor layer and having a first portion that contacts the first region; a second portion that contacts the well region and that has a thickness that is the same as that of the first portion; and a third portion that contacts the second region and that has a thickness that is greater than that of the first portion; and a gate electrode formed on the gate insulating film and opposed to the channel region where a channel is formed through the gate insulating film.

Claims

1. A semiconductor device, comprising:

a semiconductor layer that is a first conductivity type semiconductor layer;

a well region that is a second conductivity type well region formed on a surface layer portion of the semiconductor layer and that has a channel region defined therein;

a source region that is a first conductivity type source region formed on a surface layer portion of the well region and that includes a first region defined adjacent to the well region and a second region defined adjacent to the first region;

a gate insulating film formed on the semiconductor layer and having defined therein;

a first portion that contacts the first region of the source region;

a second portion that contacts the well region and that has a thickness that is the same as that of the first portion; and

a third portion that contacts the second region of the source region and that has a thickness that is greater than that of the first portion; and

a gate electrode formed on the gate insulating film and opposed to the channel region of the well region where a channel is formed through the gate insulating film,

wherein the interface between the semiconductor layer and the gate insulating film is hydrogen-terminated.

2. The semiconductor device according to claim 1, wherein the gate insulating film has a thickness which varies between the surface of the first region of the source region and the surface of the second region of the source region so that a step difference is formed and the third portion of the gate insulating film has a thickness that is greater than that of the first portion of the gate insulating film.

3. The semiconductor device according to claim 1, wherein the source region and the channel region are adjacently formed in a direction along the upper surface of the semiconductor layer, and the gate insulating film is formed on the upper surface of the semiconductor layer.

4. The semiconductor device according to claim 1, wherein the source region and the channel region are adjacently formed in a direction orthogonal to the upper surface of the semiconductor layer, wherein a trench is formed in the semiconductor layer that extends downwardly from the upper surface of the source region to pass through the source region and the well region, and wherein the gate insulating film is formed on the inner surface of the trench.

5. The semiconductor device according to claim 1, wherein the first region of the source region has an impurity concentration that is less than that of the second region of the source region.

6. The semiconductor device according to claim 1, further comprising a contact region that is a second conductivity type contact region formed to pass through both the first region and the second region of the source region.

7. A semiconductor device, comprising:

a semiconductor layer that is a first conductivity type semiconductor layer;

a well region that is a second conductivity type well region formed on a surface layer portion of the semiconductor layer and having a channel region defined therein;

a source region that is a first conductivity type source region formed on a surface layer portion of the well region and that includes a first region defined adjacent to the well region and a second region defined adjacent to the first region, the first region having an impurity concentration that is lower than that of the second region;

a gate insulating film formed on the semiconductor layer and having defined therein;

a first portion that contacts the first region of the source region;

a second portion that contacts the well region and that has a thickness that is the same as that of the first portion; and

a third portion that contacts the second region and that has a thickness that is greater than that of the first portion; and

a gate electrode formed on the gate insulating film and opposed to the channel region of the well region where a channel is formed through the gate insulating film,

wherein a drain metal is formed on the lower surface side of the semiconductor layer.

8. The semiconductor device according to claim 7, wherein the gate insulating film has a thickness which varies between the surface of the first region of the source region and the surface of the second region of the source region so that a step difference is formed and the third portion of the gate insulating film has a thickness that is greater than that of the first portion of the gate insulating film.

9. The semiconductor device according to claim 7, wherein the source region and the channel region are adjacently formed in a direction along the upper surface of the semiconductor layer, and wherein the gate insulating film is formed on the upper surface of the semiconductor layer.

10. The semiconductor device according to claim 7, wherein the source region and the channel region are adjacently formed in a direction orthogonal to the upper surface of the semiconductor layer, wherein a trench is formed in the semiconductor layer that extends downwardly from the upper surface of the source region to pass through the source region and the well region, and wherein the gate insulating film is formed on the inner surface of the trench.

11. The semiconductor device according to claim 7, further comprising a contact region that is a second conductivity type contact region formed to pass through both of the first region and the second region of the source region.