Semiconductor device

• US 9,496,413 B2
• Filed: 02/25/2016
• Issued: 11/15/2016
• Est. Priority Date: 05/01/2012
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Tsubuku, Masashi, Nonaka, Yusuke, Ishihara, Noritaka, Oota, Masashi, Kishida, Hideyuki
• Primary Examiner(s): Nguyen, Dao H
• Application Number:
  US15/053,594
• Publication Number:
  US 20160181432A1
• Time in Patent Office: 264 Days
• Field of Search: 438/104, 438/161, 438/301, 438/734, 257/43, 257/57, 257/288, 257/774, 257/E21.409, 257/E21.473, 257/E21.476, 257/E29.094, 257/E29.255, 257/E29.296
• US Class Current: 1/1
• CPC Class Codes: H01L 21/02565 Oxide semiconducting materials not being Group 12/16 materials, e.g. ternary compounds
• CPC Class Codes: H01L 21/477 Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering H01L21/38 - H01L21/449 and H01L21/461 - H01L21/475 take precedence
• CPC Class Codes: H01L 29/045 by their particular orientation of crystalline planes
• CPC Class Codes: H01L 29/4908 for thin film semiconductor, e.g. gate of TFT
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/786 Thin film transistors, i.e. transistors with a channel being at least partly a thin film transistors having only the source or the drain region on an insulator layer H01L29/0653; thin film FinFETs H01L29/785
• CPC Class Codes: H01L 29/78603 characterised by the insulating substrate or support H01L29/78657 takes precedence
• CPC Class Codes: H01L 29/78606 with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device H01L29/78642, H01L29/78645 take precedence
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

Reducing hydrogen concentration in a channel formation region of an oxide semiconductor is important in stabilizing threshold voltage of a transistor including an oxide semiconductor and improving reliability. Hence, hydrogen is attracted from the oxide semiconductor and trapped in a region of an insulating film which overlaps with a source region and a drain region of the oxide semiconductor. Impurities such as argon, nitrogen, carbon, phosphorus, or boron are added to the region of the insulating film which overlaps with the source region and the drain region of the oxide semiconductor, thereby generating a defect. Hydrogen in the oxide semiconductor is attracted to the defect in the insulating film. The defect in the insulating film is stabilized by the presence of hydrogen.

Claims

1. A method for making a semiconductor device comprising the steps of:

forming a gate electrode;

forming an insulating layer over the gate electrode;

forming an oxide semiconductor layer over the insulating layer; and

performing a heat treatment so that hydrogen in the oxide semiconductor layer moves into the insulating layer,

wherein the insulating layer and the oxide semiconductor layer comprise hydrogen, and

wherein a peak of a concentration profile of the hydrogen in the insulating layer and the oxide semiconductor layer is located in the insulating layer after the step of performing the heat treatment.

2. The method for making a semiconductor device according to claim 1, wherein the oxide semiconductor layer comprises a crystal.

3. The method for making a semiconductor device according to claim 2, wherein a c-axis of the crystal is aligned in a direction parallel to a normal vector of a surface where the oxide semiconductor layer is formed or a normal vector of a surface of the oxide semiconductor layer.

4. The method for making a semiconductor device according to claim 2, wherein the crystal is a microcrystal.

5. The method for making a semiconductor device according to claim 1, further comprising:

a source electrode electrically connected to the oxide semiconductor layer; and

a drain electrode electrically connected to the oxide semiconductor layer,

wherein the source electrode and the drain electrode is provided between the insulating layer and the oxide semiconductor layer.

6. The method for making a semiconductor device according to claim 1, further comprising:

a source electrode electrically connected to the oxide semiconductor layer; and

a drain electrode electrically connected to the oxide semiconductor layer,

wherein the source electrode and the drain electrode is provided over the oxide semiconductor layer.

7. A method for making a semiconductor device comprising the steps of:

forming a gate electrode;

forming an insulating layer over the gate electrode;

forming an oxide semiconductor layer including a channel formation region over the insulating layer; and

performing a heat treatment so that hydrogen in the oxide semiconductor layer moves into the insulating layer,

wherein the insulating layer and the oxide semiconductor layer comprise hydrogen,

wherein a peak of a concentration profile of the hydrogen in the insulating layer and the oxide semiconductor layer is located in the insulating layer after the step of performing the heat treatment,

wherein the insulating layer includes a first region and a second region,

wherein the first region and the channel formation region overlap each other,

wherein the second region and the channel formation region do not overlap each other, and

wherein a hydrogen concentration in the second region is higher than a hydrogen concentration in the first region after the step of performing the heat treatment.

8. The method for making a semiconductor device according to claim 7, wherein the oxide semiconductor layer comprises a crystal.

9. The method for making a semiconductor device according to claim 8, wherein a c-axis of the crystal is aligned in a direction parallel to a normal vector of a surface where the oxide semiconductor layer is formed or a normal vector of a surface of the oxide semiconductor layer.

10. The method for making a semiconductor device according to claim 8, wherein the crystal is a microcrystal.

11. The method for making a semiconductor device according to claim 7, further comprising:

a source electrode electrically connected to the oxide semiconductor layer; and

a drain electrode electrically connected to the oxide semiconductor layer,

wherein the source electrode and the drain electrode is provided between the insulating layer and the oxide semiconductor layer.

12. The method for making a semiconductor device according to claim 7, further comprising:

a source electrode electrically connected to the oxide semiconductor layer; and

a drain electrode electrically connected to the oxide semiconductor layer,

wherein the source electrode and the drain electrode is provided over the oxide semiconductor layer.