Solderable top metal for silicon carbide semiconductor devices

• US 9,496,421 B2
• Filed: 07/01/2008
• Issued: 11/15/2016
• Est. Priority Date: 10/21/2004
• Status: Active Grant

• Current Assignee: Siliconix Technology CV (Vishay Intertechnology Incorporated)
• Original Assignee: Siliconix Technology CV (Vishay Intertechnology Incorporated)
• Inventors: Carta, Rossano, Bellemo, Laura, Merlin, Luigi
• Primary Examiner(s): Ha, Nathan W
• Application Number:
  US12/166,309
• Publication Number:
  US 20080286968A1
• Time in Patent Office: 3,059 Days
• Field of Search: 257/762, 257/736, 257/680, 257/E21.159, 257/737, 438612-615, 438/683, 438/685, 438/687, 438/410, 438/141
• US Class Current: 1/1
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/0558 being stacked
• CPC Class Codes: H01L 2224/05639 Silver [Ag] as principal constituent
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/37124 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/37599 Material
• CPC Class Codes: H01L 23/3192 Multilayer coating
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/12 Structure, shape, material or disposition of the bump connectors prior to the connecting process
• CPC Class Codes: H01L 24/15 Structure, shape, material or disposition of the bump connectors after the connecting process
• CPC Class Codes: H01L 24/34 Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/37 of an individual strap connector
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/417 carrying the current to be rectified, amplified or switched
• CPC Class Codes: H01L 29/47 Schottky barrier electrodes H01L29/435 takes precedence
• CPC Class Codes: H01L 29/872 Schottky diodes
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00013 Fully indexed content
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01007 : Nitrogen [N]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01023 : Vanadium [V]
• CPC Class Codes: H01L 2924/01024 : Chromium [Cr]
• CPC Class Codes: H01L 2924/01028 : Nickel [Ni]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01055 : Cesium [Cs]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/05042 : Si3N4
• CPC Class Codes: H01L 2924/10272 : Silicon Carbide [SiC]
• CPC Class Codes: H01L 2924/12032 : Schottky diode
• CPC Class Codes: H01L 2924/13032 : SITh - Static Induction Thyristor, or FCTh - Field Controlled Thyristor - containing a gate structure that can shut down anode current flow
• CPC Class Codes: H01L 2924/1306 : Field-effect transistor [FET]
• CPC Class Codes: H01L 2924/13062 : Junction field-effect transistor [JFET]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]

Abstract

A silicon carbide device includes at least one power electrode on a surface thereof, a solderable contract formed on the power electrode, and at least one passivation layer that surrounds the solderable contact but is spaced from the solderable contract, thereby forming a gap.

Claims

1. A method of forming a semiconductor device comprising:

forming an electrode on a semiconductor substrate;

forming a passivation layer on the semiconductor substrate and disposed on an outer peripheral edge of the electrode; and

forming a solderable contact on the electrode spaced apart from the passivation layer to form a gap between the passivation layer and the solderable contact,

wherein the gap exposes a surface of the electrode between the passivation layer and the solderable contact.

2. The method according to claim 1, wherein the semiconductor substrate comprise silicon carbide.

3. The method according to claim 2, wherein the solderable contact comprises silver.

4. The method according to claim 3, wherein the solderable contact comprises a trimetal stack including the silver.

5. The method according to claim 4, further comprising applying a solder layer to the solderable contact.

6. The method according to claim 5, further comprising reflowing the solder layer to couple a leadframe, clip or strap to the solderable contact.

7. The method according to claim 5, wherein the gap prevents the solder from extending to the passivation layer as the solder is reflowed.

8. The method according to claim 7, wherein reflowing the solder dissolves exposed silver along the surfaces of the solderable contact to form a solder alloy.

9. The method according to claim 8, wherein the silver is captured in the solder alloy to reduce silver ion electromigration.

10. The method according to claim 8, wherein the silver is captured in the solder alloy to reduce formation of dendrites over the passivation layer.

11. The method according to claim 8, further comprising forming a second passivation layer on the passivation layer spaced apart from the sides and edges of the solderable contact to further form the gap between the second passivation layer and the solderable contact.

12. The method according to claim 11, wherein:

the passivation layer comprises an amorphous silicon; and

the second passivation layer comprises a polyimide, a phosphor silicate glass oxide or a silicon nitride.

13. A method of forming a semiconductor device comprising:

forming an electrode on a silicon carbide substrate;

forming a passivation layer on the substrate and disposed on an outer peripheral edge of the electrode; and

forming a solderable contact including silver on the electrode, spaced apart from the passivation layer to form a gap that separates the passivation layer from the solderable contact, wherein the gap surrounds the periphery of the solderable contact.

applying a solderable metal layer over the top surface of the device; and

etching the solderable metal layer to form solderable contact on the electrode within the gap.

14. The method according to claim 13, further comprising:

applying solder to the solderable contact;

reflowing the solder to couple the solderable contact to a leadframe, clip or strap.

15. The method according to claim 14, wherein the gap contains the solder inside the area of the solderable contact as the solder is reflowed.

16. The method according to claim 14, wherein the gap prevents the solder from extending into the termination region as the solder is reflowed.

17. The method according to claim 14, wherein the gap exposes the top and side surfaces of the solderable contact to prevent the passivation layer from concealing the top and side surfaces of the solderable contact.

18. The method according to claim 14, wherein reflowing solder dissolves exposed silver along the surfaces of the solderable contact to form a solder alloy.

19. The method according to claim 18, wherein the silver is captured in the solder alloy to reduce silver ion electromigration.

20. The method according to claim 18, wherein the silver is captured in the solder alloy to reduce formation of dendrites over the passivation layer.