Omnibus logic element
First Claim
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1. An integrated circuit (IC) comprising:
- a plurality of logic elements arranged in an array, each of the logic elements including;
an input-port component receiving a plurality of inputs,a programmable logic function component including a first look-up table and a second look-up table sharing the plurality of inputs,a fixed logic function component that performs an arithmetic function and couples to at least one of the plurality of inputs, wherein the fixed logic function component contains one or both of a binary adder function and a ternary adder function,wherein;
the logic element can be further configured to connect one or both of(i) outputs of the programmable logic function component to inputs of the binary adder function; and
(ii) outputs of the programmable logic function component, along with signals taken from adjacent logic elements in the array, to the ternary adder function to perform ternary addition, wherein the signals from adjacent logic elements are routed to additional input ports in an input region of the logic element and the logic element uses these input ports for ternary addition.
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Abstract
Disclosed is a logic element (LE) that can provide a number of advantageous features. For example, the LE can provide efficient and flexible use of LUTs and input sharing. The LE may also provide for flexible use of one or more dedicated adders and include register functionality.
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Citations
20 Claims
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1. An integrated circuit (IC) comprising:
a plurality of logic elements arranged in an array, each of the logic elements including; an input-port component receiving a plurality of inputs, a programmable logic function component including a first look-up table and a second look-up table sharing the plurality of inputs, a fixed logic function component that performs an arithmetic function and couples to at least one of the plurality of inputs, wherein the fixed logic function component contains one or both of a binary adder function and a ternary adder function, wherein; the logic element can be further configured to connect one or both of (i) outputs of the programmable logic function component to inputs of the binary adder function; and (ii) outputs of the programmable logic function component, along with signals taken from adjacent logic elements in the array, to the ternary adder function to perform ternary addition, wherein the signals from adjacent logic elements are routed to additional input ports in an input region of the logic element and the logic element uses these input ports for ternary addition. - View Dependent Claims (2, 3, 4, 5, 6)
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7. An integrated circuit (IC) comprising:
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a plurality of logic elements arranged in an array, each of the logic elements including an input-port component receiving a plurality of inputs, a programmable logic function component including a first look-up table and a second look-up table sharing the plurality of inputs, a fixed logic function component, wherein the programmable logic function component is an n-input lookup-table (LUT) containing 2n bits of LUT-mask; and each logic element is configured to perform a plurality of logic functions, and wherein one of the logic functions performed by each logic element is an incomplete LUT function implementing a partial function of more than n inputs. - View Dependent Claims (8, 9, 10, 11, 12, 13, 14)
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15. An integrated circuit (IC) comprising:
a plurality of logic elements arranged in an array, each of the logic elements including; an input-port component receiving a plurality of inputs, a programmable logic function component including a first look-up table and a second look-up table sharing the plurality of inputs, a fixed logic function component that performs an arithmetic function and couples to at least one of the plurality of inputs, wherein the fixed logic function component contains one or both of a binary adder function and a ternary adder function, wherein; the logic element can be further configured to connect one or both of (i) outputs of the programmable logic function component to inputs of the binary adder function; and (ii) outputs of the programmable logic function component, along with signals taken from adjacent logic elements in the array, to the ternary adder function to perform ternary addition, wherein each logic element is further configurable to implement a shift register between a first register and a second register in the logic element. - View Dependent Claims (16, 17, 18, 19, 20)
Specification