Multiphase clock data recovery for a 3-phase interface

• US 9,496,879 B1
• Filed: 09/01/2015
• Issued: 11/15/2016
• Est. Priority Date: 09/01/2015
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Chou, Shih-Wei, Duan, Ying, Lee, Chulkyu, Dang, Harry, Kwon, Ohjoon
• Primary Examiner(s): Yu, Lihong
• Application Number:
  US14/842,644
• Time in Patent Office: 441 Days
• Field of Search: 375/376
• US Class Current: 1/1
• CPC Class Codes: H03L 7/0807 concerning mainly a recovery circuit for the reference signal
• CPC Class Codes: H03L 7/0812 and where no voltage or current controlled oscillator is used
• CPC Class Codes: H04L 25/4917 using multilevel codes
• CPC Class Codes: H04L 7/0037 Delay of clock signal
• CPC Class Codes: H04L 7/0087 Preprocessing of received signal for synchronisation, e.g. by code conversion, pulse generation or edge detection
• CPC Class Codes: H04L 7/033 using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
• CPC Class Codes: H04L 7/0331 with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock H04L7/0337 takes precedence
• CPC Class Codes: H04L 7/04 Speed or phase control by synchronisation signals H04L7/0075 takes precedence

Abstract

Methods, apparatus, and systems for data communication over a multi-wire, multi-phase interface are disclosed. A method of data communication includes configuring a clock recovery circuit to provide a first clock signal that includes a pulse for each symbol transmitted on the interface, where symbols are transmitted on the interface at a first frequency, adjusting a loop delay of the clock recovery circuit to modify the first clock to have a second frequency that is no more than half the first frequency, where the clock recovery circuit generates a pulse in the first clock signal for a first of an integer number of symbols and suppresses pulse generation for other symbols in the integer number of symbols, configuring a clock generation circuit to provide a second clock signal, and capturing symbols from the interface using the first clock signal and the second clock signal.

Claims

1. A method of data communications, comprising:

configuring a clock recovery circuit to provide a first clock signal that includes pulses corresponding to symbols transmitted on a 3-wire, 3-phase interface, wherein symbols are transmitted on the 3-wire, 3-phase interface at a first frequency;

adjusting a loop delay of the clock recovery circuit to modify the first clock to have a second frequency that is no more than half the first frequency, wherein the clock recovery circuit generates a pulse in the first clock signal for a first of an integer number of symbols and suppresses pulse generation for other symbols in the integer number of symbols;

configuring a clock generation circuit to provide a second clock signal, wherein the second clock signal includes pulses for each of the other symbols in the integer number of symbols; and

capturing symbols from the 3-wire, 3-phase interface using the first clock signal and the second clock signal,

wherein the loop delay corresponds to a pulse generation cycle used to generate a pulse in response to a first-detected transition in signaling state of the 3-wire, 3-phase interface, and

wherein detection of other transitions in signaling state of the 3-wire, 3-phase interface is suppressed during the pulse generation cycle.

2. The method of claim 1, wherein adjusting the loop delay comprises:

configuring a programmable delay circuit.

3. The method of claim 1, wherein the first frequency is twice the second frequency, and wherein the second clock signal includes one pulse for every pulse in the first clock signal.

4. The method of claim 3, wherein the second clock signal is 180 degrees phase-shifted with respect to the first clock signal.

5. The method of claim 1, wherein the second frequency is one-third of the first frequency, and wherein the second clock signal includes two pulses for every pulse in the first clock signal.

6. The method of claim 1, wherein the second frequency is one-fourth of the first frequency, and wherein the second clock signal includes three pulses for every pulse in the first clock signal.

7. The method of claim 1, wherein adjusting the loop delay of the clock recovery circuit includes:

configuring a first circuit to recover a reference clock signal from a stream of symbols received from the 3-wire, 3-phase interface, wherein the reference clock signal has a frequency corresponding to the first frequency;

determining a current frequency of the first clock signal by comparing frequencies of the reference clock signal and the first clock signal during each of a plurality of calibration cycles;

increasing the loop delay when the current frequency is determined to be greater than the second frequency;

decreasing the loop delay when the current frequency is determined to be less than the second frequency; and

terminating the plurality of calibration cycles when the current frequency is determined to be equal to the second frequency.

8. An apparatus for decoding data transmitted on a 3-wire 3-phase interface, comprising:

means for configuring a clock recovery circuit to provide a first clock signal that includes pulses corresponding to symbols transmitted at a first frequency on a 3-wire, 3-phase interface;

means for calibrating a loop delay of the clock recovery circuit, wherein in one mode of operation, the means for calibrating the loop delay modifies the first clock signal to have a second frequency that is no more than half the first frequency, wherein the clock recovery circuit generates a pulse in the first clock signal for a first of an integer number of symbols and suppresses pulse generation for other symbols in the integer number of symbols;

means for configuring a clock generation circuit to provide a second clock signal, wherein the second clock signal includes pulses for each of the other symbols in the integer number of symbols; and

means for capturing symbols from the 3-wire, 3-phase interface using the first clock signal and the second clock signal,

wherein the loop delay corresponds to a pulse generation cycle used to generate a pulse in response to a first-detected transition in signaling state of the 3-wire, 3-phase interface, and

wherein detection of other transitions in signaling state of the 3-wire, 3-phase interface is suppressed during the pulse generation cycle.

9. The apparatus of claim 8, wherein the means for calibrating the loop delay is configured to:

program a programmable delay circuit.

10. The apparatus of claim 8, wherein the first frequency is twice the second frequency, and wherein the second clock signal includes one pulse for every pulse in the first clock signal, and wherein the second frequency is 180 degrees phase-shifted with respect to the first clock signal.

11. The apparatus of claim 8, wherein the second frequency is one-third of the first frequency, and wherein the second clock signal includes two pulses for every pulse in the first clock signal.

12. The apparatus of claim 8, wherein the second frequency is one-fourth of the first frequency, and wherein the second clock signal includes three pulses for every pulse in the first clock signal.

13. The apparatus of claim 8, wherein the means for calibrating the loop delay of the clock recovery circuit is configured to:

cause a first circuit to recover a reference clock signal from a stream of symbols received from the 3-wire, 3-phase interface, wherein the reference clock signal has a frequency corresponding to a rate of transmission of the stream of symbols;

determine a current frequency of the first clock signal by comparing frequencies of the reference clock signal and the first clock signal during each of a plurality of calibration cycles;

increase the loop delay when the current frequency is determined to be greater than the second frequency;

decrease the loop delay when the current frequency is determined to be less than the second frequency; and

terminate the plurality of calibration cycles when the current frequency is determined to be equal to the second frequency.

14. An apparatus for data communication, comprising:

a plurality of difference receivers coupled to a 3-wire bus;

a clock recovery circuit configured to provide a first clock signal that includes pulses corresponding to symbols transmitted in a stream of symbols at a first frequency on a 3-wire, 3-phase interface; and

a processing circuit configured to;

adjust a loop delay of the clock recovery circuit until the first clock is modified to have a second frequency that is no more than half the first frequency, wherein the clock recovery circuit generates a pulse in the first clock signal for a first of an integer number of symbols in the stream of symbols and suppresses pulse generation for other symbols in the integer number of the stream of symbols; and

configure a clock generation circuit to provide a second clock signal, wherein the second clock signal includes pulses for each of the other symbols in the integer number of symbols; and

one or more registers that capture symbols from the 3-wire, 3-phase interface in response to pulses in the first clock signal and the second clock signal,

wherein the loop delay corresponds to a pulse generation cycle used to generate a pulse in response to a first-detected transition in signaling state of the 3-wire, 3-phase interface, and

wherein detection of other transitions in signaling state of the 3-wire, 3-phase interface is suppressed during the pulse generation cycle.

15. The apparatus of claim 14, wherein the processing circuit adjusts the loop delay of the clock recovery circuit by configuring a programmable delay circuit.

16. The apparatus of claim 14, wherein the first frequency is twice the second frequency, and wherein the second clock signal includes one pulse for every pulse in the first clock signal.

17. The apparatus of claim 14, wherein the second frequency is one-third of the first frequency, and wherein the second clock signal includes two pulses for every pulse in the first clock signal.

18. The apparatus of claim 14, wherein the second frequency is one-fourth of the first frequency, and wherein the second clock signal includes three pulses for every pulse in the first clock signal.

19. The apparatus of claim 14, wherein the processing circuit adjusts the loop delay of the clock recovery circuit by:

configuring a first circuit to recover a reference clock signal from a stream of symbols received from the 3-wire, 3-phase interface, wherein the reference clock signal has a frequency corresponding to a rate of transmission of the stream of symbols;

determining a current frequency of the first clock signal by comparing frequencies of the reference clock signal and the first clock signal during each of a plurality of calibration cycles;

increasing the loop delay when the current frequency is determined to be greater than the second frequency;

decreasing the loop delay when the current frequency is determined to be less than the second frequency; and

terminating the plurality of calibration cycles when the current frequency is determined to be equal to the second frequency.

20. A processor readable storage medium, comprising code for:

configuring a clock recovery circuit to provide a first clock signal that includes pulses corresponding to symbols transmitted on a 3-wire, 3-phase interface, wherein symbols are transmitted on the 3-wire, 3-phase interface at a first frequency;

adjusting a loop delay of the clock recovery circuit such that the first clock has a second frequency that is no more than half the first frequency, wherein the clock recovery circuit generates a pulse in the first clock signal for a first of an integer number of symbols and suppresses pulse generation for other symbols in the integer number of symbols;

configuring a clock generation circuit to provide a second clock signal, wherein the second clock signal includes pulses for each of the other symbols in the integer number of symbols; and

capturing symbols from the 3-wire, 3-phase interface using the first clock signal and the second clock signal,

wherein the loop delay corresponds to a pulse generation cycle used to generate a pulse in response to a first-detected transition in signaling state of the 3-wire, 3-phase interface, and

wherein detection of other transitions in signaling state of the 3-wire, 3-phase interface is suppressed during the pulse generation cycle.

21. The storage medium of claim 20, wherein adjusting the loop delay includes configuring a programmable delay circuit.

22. The storage medium of claim 20, wherein the first frequency is twice the second frequency, and wherein the second clock signal includes one pulse for every pulse in the first clock signal, wherein the second clock signal is 180 degrees phase-shifted with respect to the first clock signal.

23. The storage medium of claim 20, wherein the second frequency is one-third of the first frequency, and wherein the second clock signal includes two pulses for every pulse in the first clock signal.

24. The storage medium of claim 20, wherein the second frequency is one-fourth of the first frequency, and wherein the second clock signal includes three pulses for every pulse in the first clock signal.

25. The storage medium of claim 20, wherein adjusting the loop delay of the clock recovery circuit includes:

configuring a first circuit to recover a reference clock signal from a stream of symbols received from the 3-wire, 3-phase interface, wherein the reference clock signal has a frequency corresponding to a rate of transmission of the stream of symbols;

determining a current frequency of the first clock signal by comparing frequencies of the reference clock signal and the first clock signal during each of a plurality of calibration cycles;

increasing the loop delay when the current frequency is determined to be greater than the second frequency;

decreasing the loop delay when the current frequency is determined to be less than the second frequency; and

terminating the plurality of calibration cycles when the current frequency is determined to be equal to the second frequency.