Integrated circuit providing fault prediction

• US 9,500,705 B2
• Filed: 08/28/2013
• Issued: 11/22/2016
• Est. Priority Date: 08/28/2013
• Status: Active Grant

• Current Assignee: Wisconsin Alumni Research Foundation (University of Wisconsin System)
• Original Assignee: Wisconsin Alumni Research Foundation (University of Wisconsin System)
• Inventors: Balasubramanian, Raghuraman, Sankaralingam, Karthikeyan
• Primary Examiner(s): Nguyen, Tung X
• Assistant Examiner(s): Zakaria, Akm
• Application Number:
  US14/012,255
• Publication Number:
  US 20150061707A1
• Time in Patent Office: 1,182 Days
• Field of Search: 324/750.01, 324/750.3, 324/750.05, 714/721, 714/738, 714/735, 714/16, 714/54, 714/726, 714/733, 714/746, 714/30, 713/100, 713/375
• US Class Current: 1/1
• CPC Class Codes: G01R 31/2856 Internal circuit aspects, e.g. built-in test features; Test chips; Measuring material aspects, e.g. electro migration [EM]
• CPC Class Codes: G01R 31/31725 Timing aspects, e.g. clock distribution, skew, propagation delay for tester hardware G01R31/31937

Abstract

The prediction of hardware failure is obtained by operating two redundant circuit modules while one circuit module is artificially aged. The output of the two circuit modules is compared and a discrepancy between outputs indicates a projected failure of the aged modules. Aging may be accomplished by one or a combination of lowering operating voltages and re-phasing a sampling clock to reduce slack time both of which provide increased sensitivity to gate delay.

Claims

1. An integrated circuit comprised of multiple gates subject to increased gate delay with age, the integrated circuit comprising:

at least a first and second redundant circuit module concurrently generating first and second respective outputs; and

a reliability circuitry operating to;

(a) momentarily and selectively apply a stress to the first redundant circuit module in a manner mimicking age-increased gate delay which changes the first output of the first redundant circuit module compared to the second output of the second redundant circuit module without applying the stress to the second redundant circuit module, the stress including at least one of;

(i) decreasing an operating voltage of gates of the first redundant circuit module relative to an operating voltage of gates of the second redundant circuit module, and (ii) decreasing a slack time in a capture of a signal of the first redundant circuit module relative to a capture of a corresponding signal of the second redundant circuit module;

(b) capture first and second values based on the respective first changed output and second output from the first and second redundant circuit modules during the stressing; and

(c) compare the captured first and second values to detect errors caused by the selective stressing.

2. The integrated circuit of claim 1 wherein the captured first and second values are latched outputs of logical gates.

3. The integrated circuit of claim 1 wherein steps (a)-(c) are repeated.

4. The integrated circuit of claim 3 wherein steps (a)-(c) are completed during an interval and wherein a duration of the interval is less than 1/10 of a time between periodic repetitions of steps (a)-(c).

5. The integrated circuit of claim 3 wherein at different periodic repetitions, steps (a)-(c) are varied to stress the second redundant circuit module without a stressing of the first redundant circuit module.

6. The integrated circuit of claim 1 wherein the stress is induced by lowering an operating voltage of the gates of the first redundant circuit module relative to an operating voltage of the gates of the second redundant circuit module.

7. The integrated circuit of claim 1 wherein the stress is induced by decreasing a slack time in a capture of at least some of the outputs from the first redundant circuit module relative to a capture of the outputs of the second redundant circuit module.

8. The integrated circuit of claim 7 wherein the slack time is decreased by changing a phase of a clock controlling capture of the at least some of the outputs relative to a phase of a clock controlling inputs to the gates.

9. The integrated circuit of claim 7 wherein the stress is induced for a first portion of the first redundant circuit module by decreasing a slack time in a capture of at least some of the output from the first portion of the first redundant circuit module relative to a capture of corresponding outputs from a corresponding first portion of the second redundant circuit module;

and

wherein the stress is induced for a second portion of the first redundant circuit module by decreasing an operating voltage of gates of the second portion of the first redundant circuit module relative to an operating voltage of gates of a corresponding second portion of the second redundant circuit module.

10. The integrated circuit of claim 1 wherein the first and second redundant circuit modules are circuits synchronously driven by a clock signal and wherein the capturing is performed by latches synchronized in frequency to the clock signal.

11. The integrated circuit of claim 1 wherein the stress mimics an aging of at least one month.

12. The integrated circuit of claim 1 wherein the first and second redundant circuits are substantially identical.

13. The integrated circuit of claim 1 wherein the first and second redundant circuits are processor cores.

14. The integrated circuit of claim 13 wherein the reliability circuitry is a processor core.

15. The integrated circuit of claim 1 further including the step of (d) modifying operation of the integrated circuit in response to a detected error at step (c).

16. The integrated circuit of claim 15 wherein the modification of the operation of the integrated circuit slows a clock speed of the integrated circuit.

17. The integrated circuit of claim 15 wherein the modification of the operation of the integrated circuit blocks operation of predetermined critical functions from being performed on the first redundant circuit module in response to an error detected at step (c).

18. The integrated circuit of claim 1 further including the step of (d) outputting a signal to a user of the integrated circuit indicating an error detected at step (c).

20. The integrated circuit of claim 1 wherein the captured first and second values are program values derived from the first and second outputs.

19. A method of predicting failure in an integrated circuit comprised of multiple gates subject to increased gate delay with age in the integrated circuit, the method comprising the steps of:

(a) momentarily and selectively stressing a first redundant circuit module of the integrated circuit in a manner mimicking age-increased gate delay which changes the output of the first redundant circuit module compared to an output of the second redundant circuit module without stressing a concurrently operating second redundant circuit module of the integrated circuit, the stressing including at least one of;

(i) decreasing an operating voltage of gates of the first redundant circuit module relative to an operating voltage of gates of the second redundant circuit module, and (ii) decreasing a slack time in a capture of a signal of the first redundant circuit module relative to a capture of a corresponding of the second redundant circuit module;

(b) capturing the first changed output and second output from first and second redundant circuit modules during the stressing; and

(c) comparing the captured outputs to detect errors caused by the selective stressing.