Liquid crystal display

• US 9,500,898 B2
• Filed: 06/20/2013
• Issued: 11/22/2016
• Est. Priority Date: 12/09/2008
• Status: Active Grant

• Current Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Original Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Inventors: Kim, Yoon-Jang, Kim, Dong-Gyu, Cho, Eun, Kwon, Yeong-Keun, Park, Kee-Bum
• Primary Examiner(s): CHANG, CHARLES S
• Application Number:
  US13/923,075
• Publication Number:
  US 20130278874A1
• Time in Patent Office: 1,251 Days
• Field of Search: 349/48
• US Class Current: 1/1
• CPC Class Codes: G02F 1/133514 Colour filters
• CPC Class Codes: G02F 1/134363 for applying an electric field parallel to the substrate, i.e. in-plane switching [IPS]
• CPC Class Codes: G02F 1/13606 having means for reducing parasitic capacitance
• CPC Class Codes: G02F 1/136213 Storage capacitors associated with the pixel electrode
• CPC Class Codes: G02F 1/136222 Colour filters incorporated in the active matrix substrate
• CPC Class Codes: G02F 1/13624 having more than one switching element per pixel

Abstract

A liquid crystal display according to an embodiment of the present invention includes: a first substrate; a plurality of color filters formed on the first substrate and arranged in a matrix with an island shape; a plurality of pixel electrodes formed on the color filters; and a capacitor disposed between neighboring color filters in a column direction among the color filters, wherein two terminals forming the capacitor are disposed at a portion outside a position overlapping the color filters.

Claims

1. A liquid crystal display, comprising:

a substrate;

a first gate line and a second gate line disposed on the substrate;

a capacitive electrode line extended substantially parallel to the first gate line and the second gate line;

a data line intersecting the first gate line and the second gate line;

a first pixel electrode including a first sub pixel electrode and a second sub pixel electrode, and a second pixel electrode disposed on the substrate;

a first thin film transistor comprising a first terminal connected to the first gate line, a second terminal connected to the data line, and a third terminal connected to the first sub pixel electrode;

a second thin film transistor comprising a first terminal connected to the first gate line, a second terminal connected to the data line, and a third terminal connected to the second sub pixel electrode;

a third thin film transistor comprising a first terminal connected to the second gate line, a second terminal connected to the second sub pixel electrode, and a third terminal connected to the capacitive electrode line; and

a third gate line connected to the second pixel electrode,

wherein the second gate line, the capacitive electrode line, and the third gate line are disposed between the first pixel electrode and the second pixel electrode and separated from the second gate line.

2. The liquid crystal display of claim 1, wherein the second gate line is disposed between the third gate line and the capacitive electrode line.

3. The liquid crystal display of claim 1, wherein a voltage of the second sub pixel electrode is lower than a voltage of the first sub pixel electrode.

4. The liquid crystal display of claim 3, wherein the second sub pixel electrode is adjacent to the capacitive electrode line.

5. The liquid crystal display of claim 3, wherein the first sub pixel electrode is adjacent to the first gate line.

6. The liquid crystal display of claim 3, wherein the third thin film transistor is turned on after the first and second thin film transistors are turned on.

7. A liquid crystal display, comprising:

a substrate;

a plurality of first gate lines and a plurality of second gate lines disposed on the substrate;

a plurality of capacitive electrode lines extended substantially parallel to the first gate line and the second gate line;

a plurality of data lines intersecting the gate line;

a plurality of first sub pixel electrodes and a plurality of second sub pixel electrodes disposed on the substrate;

a first thin film transistor comprising a first terminal connected to the first gate line, a second terminal connected to the data line, and a third terminal connected to the first sub pixel electrode;

a second thin film transistor comprising a first terminal connected to the first gate line, a second terminal connected to the data line, and a third terminal connected to the second sub pixel electrode; and

a third thin film transistor comprising a first terminal connected to the second gate line, a second terminal connected to the second sub pixel electrode, and a third terminal connected to the capacitive electrode line,

wherein the capacitive electrode line is disposed between the second sub pixel electrode and the second gate line, and

wherein the second gate line is not connected to a thin film transistor disposed on an adjacent pixel row.

8. The liquid crystal display of claim 7, wherein a voltage of the second sub pixel electrode is lower than a voltage of the first pixel electrode.

9. The liquid crystal display of claim 8, wherein the first sub pixel electrode is adjacent to the first gate line.

10. The liquid crystal display of claim 8, wherein the third thin film transistor is turned on after the first and second thin film transistors are turned on.

11. The liquid crystal display of claim 7, wherein the first gate line, the second gate line, and the capacitive electrode line are adjacent to one another, and

the second gate line is disposed between the first gate line and the capacitive electrode line.