Apparatus and method for processing signal

• US 9,501,090 B2
• Filed: 07/14/2015
• Issued: 11/22/2016
• Est. Priority Date: 12/23/2014
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Kim, JongPal, Lee, TakHyung
• Primary Examiner(s): HOUSTON, ADAM D
• Application Number:
  US14/798,665
• Publication Number:
  US 20160179129A1
• Time in Patent Office: 497 Days
• Field of Search: 327/144, 327147-149, 327156-158
• US Class Current: 1/1
• CPC Class Codes: G06F 1/12 Synchronisation of different clock signals provided by a plurality of clock generators

Abstract

A method and apparatus process a signal include local clock signal generators configured to, based on a reference clock signal, generate operation clock signals for analog channels and, based on a synchronizing signal, adjust a phase difference among the operation clock signals.

Claims

1. An apparatus to process a signal, comprising:

local clock signal generators configured to, based on a reference clock signal, generate operation clock signals for analog channels and, based on a synchronizing signal, adjust a phase difference among the operation clock signals,

wherein the local clock signal generators are configured to generate operation clock signals of which high logic states do not overlap in an identical time interval.

2. The apparatus of claim 1, further comprising:

a central clock signal generator configured to supply the reference clock signal and the synchronizing signal to the local clock signal generators.

3. The apparatus of claim 1, wherein the local clock signal generators are configured to generate the operation clock signals based on the synchronizing signal and subsequent to completing a register setting of the operation clock signals for the analog channels.

4. The apparatus of claim 3, wherein the local clock signal generators comprise a counter configured to output a waveform defined based on the register setting, and set a count value as a set value based on the synchronizing signal.

8. The apparatus of claim 1, wherein the operation clock signals comprise at least one of a clock signal to modulate analog signals input through the analog channels, a clock signal to demodulate the analog signals, a clock signal for filtering the analog signals, and a clock signal to sample the analog signals to be converted into digital signals.

5. An apparatus to process a signal, comprising:

local clock signal generators configured to, based on a reference clock signal, generate operation clock signals for analog channels and, based on a synchronizing signal, adjust a phase difference among the operation clock signals; and

local bias signal generators configured to generate operation bias signals for the analog channels based on a reference bias signal.

6. The apparatus of claim 5, further comprising:

a central bias signal generator configured to supply the reference bias signal.

7. The apparatus of claim 5, wherein the local bias signal generators are configured to generate operation voltage signals for the analog channels based on the reference bias signal being a current signal.

9. An apparatus to process a signal, comprising:

local clock signal generators configured to generate operation clock signals for analog channels based on a reference clock signal and subsequent to a point in time at which a reference is satisfied;

a central bias signal generator configured to supply a reference bias signal to local bias signal generators; and

local bias signal generators configured to generate operation bias signals for the analog channels based on the reference bias signal.

10. The apparatus of claim 9, further comprising:

a central clock signal generator configured to supply the reference clock signal to local clock signal generators.

11. The apparatus of claim 9, wherein the local clock signal generators are configured to generate the operation clock signals based on the reference clock signal and subsequent to completing a register setting of the operation clock signals for the analog channels.

12. The apparatus of claim 11, wherein the local clock signal generators comprise a counter configured to output a waveform defined based on the register setting, and set a count value of the counter as a set value based on a reset signal prior to a point in time at which the reference is satisfied.

13. The apparatus of claim 11, wherein the central clock signal generator is configured to supply the reference clock signal to the local clock signal generators subsequent to completing the register setting of the operation clock signals for the analog channels.

14. The apparatus of claim 9, wherein the local bias signal generators are configured to generate operation voltage signals for the analog channels based on the reference bias signal being a current signal.

15. A method to process a signal, comprising:

generating a reference clock signal and a synchronizing signal; and

generating operation clock signals, using local clock signal generators, for each of analog channels based on the reference clock signal and by adjusting a phase difference among the operation clock signals based on the synchronizing signal,

wherein the generating of the operation clock signals comprises generating operation clock signals of which high logic states do not overlap in an identical time interval.

16. The method of claim 15 wherein the generating of the operation clock signals comprises generating the operation clock signals based on the synchronizing signal subsequent to completing a register setting of the operation clock signals for the analog channels.

17. The method claim 15, wherein the operation clock signals comprise at least one of a clock signal to modulate analog signals input through the analog channels, a clock signal to demodulate the analog signals, a clock signal to filter the analog signals, and a clock signal to sample the analog signals to be converted into digital signals.