Voltage detection system and controlling method of the same

• US 9,501,113 B2
• Filed: 06/20/2011
• Issued: 11/22/2016
• Est. Priority Date: 06/21/2010
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Electronics Corporation
• Inventors: Kouno, Kyouhei, Yamaguchi, Kazuyo, Nakatsu, Shinichi, Eto, Kimiharu, Ishihara, Kuniyasu, Shimoda, Hirotaka, Urakawa, Yuusuke, Indo, Seiya
• Primary Examiner(s): Henson, Mischita
• Assistant Examiner(s): BLOSS, STEPHANIE E
• Application Number:
  US13/164,405
• Publication Number:
  US 20110313700A1
• Time in Patent Office: 1,982 Days
• Field of Search: 702/64, 327/142, 327/143, 327/198
• US Class Current: 1/1
• CPC Class Codes: G06F 1/24 Resetting means
• CPC Class Codes: G06F 1/30 Means for acting in the event of power-supply failure or interruption, e.g. power-supply fluctuations for resetting only G06F1/24

Abstract

There is a need to solve a possible system malfunction when a power supply voltage decreases steeply. To solve this problem, a control method is provided for a voltage detection system having an interrupt mode and a reset mode. First and second detection levels are configured. When a power supply voltage is higher than the first detection level, a latch circuit is placed in a first state to enable the interrupt mode. When the power supply voltage becomes lower than or equal to the first detection level, an interrupt signal is generated to change the latch circuit from the first state to a second state and enable the reset mode. A system reset is issued when the power supply voltage becomes lower than or equal to the second detection level in the reset mode.

Claims

1. A voltage detection system comprising:

a comparison voltage generation circuit that outputs a first comparison voltage and a second comparison voltage;

a latch circuit that outputs a control signal;

a comparison voltage selection circuit that is input by both the first and second comparison voltage, and outputs either the first comparison voltage or the second comparison voltage as a detection level;

a comparator that outputs a detection signal based on the detection level and a third comparison voltage; and

a control circuit that outputs a fourth signal based on the control signal and the detection signal,

wherein the latch circuit determines whether the control signal is a low level or a high level.

2. The voltage detection system according to claim 1, wherein the comparison voltage selection circuit outputs the first comparison voltage when the control signal indicates a low level, and outputs the second comparison voltage when the control signal indicates a high level.

3. The voltage detection system according to claim 1, wherein the comparator sets the low level to the detection signal when the third comparison voltage is larger than the detection signal, and sets the high level to the detection signal when the third comparison voltage is smaller than the detection level.

4. The voltage detection system according to claim 1, further comprising:

an interrupt control circuit that outputs the detection signal as an interrupt signal when the control signal indicates the low level; and

a reset control circuit that outputs the detection signal as a reset signal when the control signal indicates the high level.

5. The voltage detection system according to claim 1, wherein the control circuit further comprises:

a data selection circuit that selects the high level data signal when the control signal indicates the low level, and selects the data signal input from the CPU when the control signal indicates the high level.

6. The voltage detection system according to claim 1, wherein a clock selection circuit is input by the interrupt signal and a clock signal, the control circuit selects the interrupt signal when the control signal is low level, and the control circuit selects the clock signal when the control signal is high level.

7. The voltage detection system according to claim 1,

wherein the latch circuit is a flip-flop circuit, and wherein the latch circuit latches the value of the data signal input to a data input terminal based on the rise of the signal input to a clock input terminal, and the latch circuit outputs the latched value as the control signal.