Techniques to perform power fail-safe caching without atomic metadata

• US 9,501,402 B2
• Filed: 02/19/2014
• Issued: 11/22/2016
• Est. Priority Date: 03/30/2009
• Status: Active Grant

• Current Assignee: SK Hynix NAND Product Solutions Corporation (SK Hynix Inc.)
• Original Assignee: Intel Corporation
• Inventors: Trika, Sanjeev N.
• Primary Examiner(s): BATAILLE, PIERRE MICHE
• Application Number:
  US14/184,256
• Publication Number:
  US 20140173190A1
• Time in Patent Office: 1,007 Days
• Field of Search: 711/141, 711/135, 711/118, 711/144, 711/145, 711/E12.003, 711/E12.042, 711/E12.052
• US Class Current: 1/1
• CPC Class Codes: G06F 11/1441 Resetting or repowering
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/0804 with main memory updating G06F12/0806 takes precedence
• CPC Class Codes: G06F 12/0815 Cache consistency protocols
• CPC Class Codes: G06F 12/0866 for peripheral storage systems, e.g. disk cache
• CPC Class Codes: G06F 12/0868 Data transfer between cache memory and other subsystems, e.g. storage devices or host systems
• CPC Class Codes: G06F 12/0871 Allocation or management of cache space
• CPC Class Codes: G06F 2212/1032 Reliability improvement, data loss prevention, degraded operation etc
• CPC Class Codes: G06F 2212/222 Non-volatile memory
• CPC Class Codes: G06F 2212/601 Reconfiguration of cache memory
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A method and system to allow power fail-safe write-back or write-through caching of data in a persistent storage device into one or more cache lines of a caching device. No metadata associated with any of the cache lines is written atomically into the caching device when the data in the storage device is cached. As such, specialized cache hardware to allow atomic writing of metadata during the caching of data is not required.

Claims

1. A method comprising:

utilizing, by a controller, at most, half of a full data storage capacity of a flash memory cache to cache data of a storage device that comprises a redundant array of independent disks (RAID) of a multicore processor computer; and

writing the data back to the RAID using a write back caching scheme, the write back caching scheme resulting in stored data in the storage device being capable of being asynchronous with cached data in flash memory cache, the cached data in the flash memory cache to be periodically flushed, prior to shutdown of the apparatus, to the storage device so as to ensure that, after completion of a flushing of the cached data to the storage device, all flushed cached data is capable of being recoverable despite improper shutdown of the apparatus;

the controller comprising both a run-time controller and a recovery controller, the run-time controller to implement caching mechanisms, the caching mechanisms including (1) detection of cache hits and cache misses and (2) queuing of caching commands and eviction commands;

the recovery controller to recover, after a failure event has occurred, cache state of cache lines in the cache;

the run-time controller and the recovery controller being comprised, at least in part, in a block storage driver of an operating system of the computer;

the run-time controller and/or the recovery controller to (1) determine, at least in part, whether processor utilization rate of the computer is below a threshold, and (2) synchronize the cached data of the cache with the stored data of the storage device when the processor utilization rate is below the threshold.

2. The method of claim 1, wherein:

in event of power failure of the cache, integrity and coherency of the data in the cache are preserved.

3. The method of claim 1, wherein:

the cache is also to cache other data of non-volatile main memory of the multicore processor computer.

4. The method of claim 1, wherein:

the computer comprises a multicore processor and a Universal Serial Bus (USB) interface; and

the processor is to communicate with the USB interface, the RAID, and the cache.

5. The method of claim 1, wherein:

the cache and the controller are comprised in a system on chip.

6. An apparatus comprising:

a flash memory cache having a full data storage capacity;

a controller to utilize, at most, half of the full data storage capacity to cache data of a storage device that comprises a redundant array of independent disks (RAID) of a multicore processor computer; and

wherein a write back caching scheme is to be used to write the data back to the RAID, the write back caching scheme resulting in stored data in the storage device being capable of being asynchronous with cached data in flash memory cache, the cached data in the flash memory cache to be periodically flushed, prior to shutdown of the apparatus, to the storage device so as to ensure that, after completion of a flushing of the cached data to the storage device, all flushed cached data is capable of being recoverable despite improper shutdown of the apparatus;

the controller comprising both a run-time controller and a recovery controller, the run-time controller to implement caching mechanisms, the caching mechanisms including (1) detection of cache hits and cache misses and (2) queuing of caching commands and eviction commands;

the recovery controller to recover, after a failure event has occurred, cache state of cache lines in the cache;

the run-time controller and the recovery controller being comprised, at least in part, in a block storage driver of an operating system of the computer;

the run-time controller and/or the recovery controller to (1) determine, at least in part, whether processor utilization rate of the computer is below a threshold, and (2) synchronize the cached data of the cache with the stored data of the storage device when the processor utilization rate is below the threshold.

7. The apparatus of claim 6, wherein:

in event of power failure of the cache, integrity and coherency of the data in the cache are preserved.

8. The apparatus of claim 6, wherein:

the cache is also to cache other data of non-volatile main memory of the multicore processor computer.

9. The apparatus of claim 6, wherein:

the computer comprises a multicore processor and a Universal Serial Bus (USB) interface; and

the processor is to communicate with the USB interface, the RAID, and the cache.

10. The apparatus of claim 6, wherein:

the cache and the controller are comprised in a system on chip.

11. Computer readable storage medium storing instructions that, when executed by a machine, result in performance of operations comprising:

utilizing, by a controller, at most, half of a full data storage capacity of a flash memory cache to cache data of a storage device that comprises a redundant array of independent disks (RAID) of a multicore processor computer; and

writing the data back to the RAID using a write back caching scheme, the write back caching scheme resulting in stored data in the storage device being capable of being asynchronous with cached data in flash memory cache, the cached data in the flash memory cache to be periodically flushed, prior to shutdown of the apparatus, to the storage device so as to ensure that, after completion of a flushing of the cached data to the storage device, all flushed cached data is capable of being recoverable despite improper shutdown of the apparatus;

the controller comprising both a run-time controller and a recovery controller, the run-time controller to implement caching mechanisms, the caching mechanisms including (1) detection of cache hits and cache misses and (2) queuing of caching commands and eviction commands;

the recovery controller to recover, after a failure event has occurred, cache state of cache lines in the cache;

the run-time controller and the recovery controller being comprised, at least in part, in a block storage driver of an operating system of the computer;

the run-time controller and/or the recovery controller to (1) determine, at least in part, whether processor utilization rate of the computer is below a threshold, and (2) synchronize the cached data of the cache with the stored data of the storage device when the processor utilization rate is below the threshold.

12. The medium of claim 11, wherein:

in event of power failure of the cache, integrity and coherency of the data in the cache are preserved.

13. The medium of claim 11, wherein:

the cache is also to cache other data of non-volatile main memory of the multicore processor computer.

14. The medium of claim 11, wherein:

the computer comprises a multicore processor and a Universal Serial Bus (USB) interface; and

the processor is to communicate with the USB interface, the RAID, and the cache.

15. The medium of claim 11, wherein:

the cache and the controller are comprised in a system on chip.