Communicating in an integrated circuit using hardware-managed virtual channels

• US 9,501,439 B1
• Filed: 01/19/2016
• Issued: 11/22/2016
• Est. Priority Date: 01/19/2016
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Fredrickson, Mark S., Willenborg, Scott M.
• Primary Examiner(s): Myers, Paul R
• Application Number:
  US15/000,895
• Time in Patent Office: 308 Days
• Field of Search: 710/113, 711203-209
• US Class Current: 1/1
• CPC Class Codes: G06F 13/362 with centralised access control
• CPC Class Codes: G06F 13/4068 Electrical coupling

Abstract

Embodiments herein describe a switchboard coupled to a system bus in an integrated circuit for managing the flow of data between different entities coupled to the bus (e.g., processing cores, accelerators, memory controllers, input/output (I/O) interfaces, and the like). The switchboard is a hardware module that may be tasked with assigning different system bus addresses (or range of addresses) to each of the entities coupled to the bus. These addresses may be unique such that each entity can be uniquely identified by its assigned address. The address space of the system bus also includes managed address that are reserved—i.e., are not assigned to any particular entity. The switchboard is tasked with assigning the managed addresses (also referred to as virtual channels) to an entity which can be used to enable direct communication between hardware entities using the system bus.

Claims

1. An integrated circuit, comprising:

a system bus configured to broadcast data to a first and a second hardware entities coupled to the system bus;

a bus manager coupled to the system bus, wherein the bus manager is configured to;

assign a managed address to the first entity based on a characteristic of the first entity, wherein the managed address is a reserved address in an address space of the system bus,

receive a request from the second entity via the system bus to perform a task using the first entity, and

provide the managed address to the second entity via the system bus, wherein the managed address enables the second entity to communicate directly with the first entity using the system bus,

wherein the first entity is assigned both a first address and the managed address in the address space of the system bus, wherein the first address is different than the managed address, and wherein the first entity is configured to;

monitor the system bus to identify data transmitted on the system bus that includes one of the first address and the managed address.

2. The integrated circuit of claim 1, wherein the first entity comprises an accelerator and the bus manager is configured to:

upon receiving the request, determine whether the accelerator is available to perform the task by comparing a function of the task to a function performed by the accelerator, wherein the managed address is provided to the second entity only if the function of the accelerator is the same as the function of the task.

3. The integrated circuit of claim 2, wherein the bus manager is configured to:

upon receiving the request, determine whether the accelerator has sufficient bandwidth to perform the task, wherein the managed address is provided to the second entity only if the accelerator has sufficient bandwidth.

4. The integrated circuit of claim 1, further comprising:

a plurality of processing cores each coupled to the system bus, wherein the second entity is one of the processing cores.

5. The integrated circuit of claim 1, wherein the bus manager is configured to:

monitor the system bus to identify data transmitted on the system bus that includes the managed address;

upon identifying data that includes the managed address, identifying a source of the data; and

upon determining the source is not authorized by the bus manager to use the managed address, prevent the source from communicating with the first entity using the managed address.

6. The integrated circuit of claim 1, wherein the bus manager is configured to:

receive a message from the first entity using the system bus, the message comprising the characteristic of the first entity.

7. The integrated circuit of claim 1, wherein the bus manager is configured to:

reassign the managed address from the first entity to a different one of the plurality of hardware entities coupled to the system bus.

8. The integrated circuit of claim 1, wherein the bus manager is configured to manage a plurality of different managed addresses which can be assigned to the plurality of hardware entities coupled to the system bus, wherein the different managed addresses supplement respective addresses that have previously been assigned to the plurality of hardware entities.

9. A processor system, comprising:

a system bus configured to broadcast data to a plurality of hardware entities communicatively coupled to the system bus;

an accelerator communicatively coupled to the system bus;

a plurality of processing cores communicatively coupled to the system bus; and

a bus manager coupled to the system bus, wherein the bus manager is configured to;

assign a managed address to the accelerator based on a characteristic of the accelerator, wherein the managed address is a reserved address in an address space of the system bus,

receive a request from one of the processing cores via the system bus to perform a task using the accelerator, and

provide the managed address to the one processing core via the system bus, wherein the managed address enables the one processing core to communicate directly with the accelerator using the system bus,

wherein the accelerator is assigned both a first address and the managed address in the address space of the system bus, wherein the first address is different than the managed address, and wherein the accelerator is configured to;

monitor the system bus to identify data transmitted on the system bus that includes one of the first address and the managed address.

10. The processor system of claim 9, comprising a plurality of integrated circuits, wherein the accelerator is disposed on a first one of the plurality of integrated circuits and the system bus and the one processing core are disposed on a second one of the plurality of integrated circuits.

11. The processor system of claim 9, wherein the bus manager is configured to:

upon receiving the request, determine whether the accelerator is available to perform the task by comparing a function of the task to a function performed by the accelerator, wherein the managed address is provided to the one processing core only if the function of the accelerator is the same as the function of the task.

12. The processor system of claim 9, wherein the bus manager is configured to:

upon receiving the request, determine whether the accelerator has sufficient bandwidth to perform the task, wherein the managed address is provided to the one processing core only if the accelerator has sufficient bandwidth.

13. The processor system of claim 9, wherein the bus manager is configured to:

monitor the system bus to identify data transmitted on the system bus that includes the managed address;

upon identifying data that includes the managed address, identifying a source of the data; and

upon determining the source is not authorized by the bus manager to use the managed address, prevent the source from communicating with the accelerator using the managed address.

14. The processor system of claim 9, wherein the bus manager is configured to manage a plurality of different managed addresses which can be assigned to different entities coupled to the system bus, wherein the different managed addresses supplement respective addresses that have already been assigned to the different entities.

15. A method, comprising:

assigning, using a bus manager coupled to a system bus, a managed address to an first hardware entity coupled to the system bus based on a characteristic of the first entity, wherein the managed address is a reserved address in an address space of the system bus;

receiving a request from a second hardware entity coupled to the system bus to perform a task using the first entity; and

providing the managed address to the second entity via the system bus, wherein the managed address enables the second entity to communicate directly with the first entity using the system bus, wherein the bus manager, system bus, first entity, and second entity are embodied within a common integrated circuit,

wherein the first hardware entity is assigned both a first address and the managed address in the address space of the system bus, wherein the first address is different than the managed address, and wherein the first hardware entity is configured to;

monitor the system bus to identify data transmitted on the system bus that includes one of the first address and the managed address.

16. The method of claim 15, wherein the first entity comprises an accelerator, the method further comprising:

upon receiving the request, determining whether the accelerator is available to perform the task by comparing a function of the task to a function performed by the accelerator, wherein the managed address is provided to the second entity only if the function of the accelerator is the same as the function of the task.

17. The method of claim 15, further comprising:

upon receiving the request, determining whether the first entity has sufficient bandwidth to perform the task, wherein the managed address is provided to the second entity only if the first entity has sufficient bandwidth.

18. The method of claim 15, further comprising:

monitoring the system bus to identify data transmitted on the system bus using the managed address;

upon identifying data transmitted using the managed address, identifying a source of the data; and

upon determining the source is not authorized to use the managed address, preventing the source from communicating with the first entity using the managed address.