Communicating in an integrated circuit using hardware-managed virtual channels
First Claim
1. An integrated circuit, comprising:
- a system bus configured to broadcast data to a first and a second hardware entities coupled to the system bus;
a bus manager coupled to the system bus, wherein the bus manager is configured to;
assign a managed address to the first entity based on a characteristic of the first entity, wherein the managed address is a reserved address in an address space of the system bus,receive a request from the second entity via the system bus to perform a task using the first entity, andprovide the managed address to the second entity via the system bus, wherein the managed address enables the second entity to communicate directly with the first entity using the system bus,wherein the first entity is assigned both a first address and the managed address in the address space of the system bus, wherein the first address is different than the managed address, and wherein the first entity is configured to;
monitor the system bus to identify data transmitted on the system bus that includes one of the first address and the managed address.
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Accused Products
Abstract
Embodiments herein describe a switchboard coupled to a system bus in an integrated circuit for managing the flow of data between different entities coupled to the bus (e.g., processing cores, accelerators, memory controllers, input/output (I/O) interfaces, and the like). The switchboard is a hardware module that may be tasked with assigning different system bus addresses (or range of addresses) to each of the entities coupled to the bus. These addresses may be unique such that each entity can be uniquely identified by its assigned address. The address space of the system bus also includes managed address that are reserved—i.e., are not assigned to any particular entity. The switchboard is tasked with assigning the managed addresses (also referred to as virtual channels) to an entity which can be used to enable direct communication between hardware entities using the system bus.
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Citations
18 Claims
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1. An integrated circuit, comprising:
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a system bus configured to broadcast data to a first and a second hardware entities coupled to the system bus; a bus manager coupled to the system bus, wherein the bus manager is configured to; assign a managed address to the first entity based on a characteristic of the first entity, wherein the managed address is a reserved address in an address space of the system bus, receive a request from the second entity via the system bus to perform a task using the first entity, and provide the managed address to the second entity via the system bus, wherein the managed address enables the second entity to communicate directly with the first entity using the system bus, wherein the first entity is assigned both a first address and the managed address in the address space of the system bus, wherein the first address is different than the managed address, and wherein the first entity is configured to; monitor the system bus to identify data transmitted on the system bus that includes one of the first address and the managed address. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A processor system, comprising:
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a system bus configured to broadcast data to a plurality of hardware entities communicatively coupled to the system bus; an accelerator communicatively coupled to the system bus; a plurality of processing cores communicatively coupled to the system bus; and a bus manager coupled to the system bus, wherein the bus manager is configured to; assign a managed address to the accelerator based on a characteristic of the accelerator, wherein the managed address is a reserved address in an address space of the system bus, receive a request from one of the processing cores via the system bus to perform a task using the accelerator, and provide the managed address to the one processing core via the system bus, wherein the managed address enables the one processing core to communicate directly with the accelerator using the system bus, wherein the accelerator is assigned both a first address and the managed address in the address space of the system bus, wherein the first address is different than the managed address, and wherein the accelerator is configured to; monitor the system bus to identify data transmitted on the system bus that includes one of the first address and the managed address. - View Dependent Claims (10, 11, 12, 13, 14)
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15. A method, comprising:
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assigning, using a bus manager coupled to a system bus, a managed address to an first hardware entity coupled to the system bus based on a characteristic of the first entity, wherein the managed address is a reserved address in an address space of the system bus; receiving a request from a second hardware entity coupled to the system bus to perform a task using the first entity; and providing the managed address to the second entity via the system bus, wherein the managed address enables the second entity to communicate directly with the first entity using the system bus, wherein the bus manager, system bus, first entity, and second entity are embodied within a common integrated circuit, wherein the first hardware entity is assigned both a first address and the managed address in the address space of the system bus, wherein the first address is different than the managed address, and wherein the first hardware entity is configured to; monitor the system bus to identify data transmitted on the system bus that includes one of the first address and the managed address. - View Dependent Claims (16, 17, 18)
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Specification