Semiconductor memory and memory system using the same

• US 9,502,136 B1
• Filed: 02/04/2016
• Issued: 11/22/2016
• Est. Priority Date: 09/17/2015
• Status: Active Grant

• Current Assignee: SK Hynix Inc.
• Original Assignee: SK Hynix Inc.
• Inventors: Kim, Kwan Weon
• Primary Examiner(s): Yang, Han
• Application Number:
  US15/015,743
• Time in Patent Office: 292 Days
• Field of Search: 365/200, 365/230.1, 365/230.05, 365/219
• US Class Current: 1/1
• CPC Class Codes: G11C 29/10 Test algorithms, e.g. memory scan [MScan] algorithms; Test patterns, e.g. checkerboard patterns
• CPC Class Codes: G11C 29/12 Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
• CPC Class Codes: G11C 29/36 Data generation devices, e.g. data inverters
• CPC Class Codes: G11C 29/46 Test trigger logic
• CPC Class Codes: G11C 29/56004 Pattern generation

Abstract

A semiconductor memory includes a memory block configured to perform an operation according to a first test pattern or a second test pattern, a switching circuit configured to provide the first test pattern or the second test pattern to the memory block according to a first test mode signal and a second test mode signal, and a test pattern setup circuit configured to store a test pattern source signal in a feedback loop varied according to a third test mode signal and output the stored test pattern source signal as the first test pattern.

Claims

1. A semiconductor memory comprising:

a memory block configured to perform an operation according to a first test pattern or a second test pattern;

a switching circuit configured to provide the first test pattern or the second test pattern to the memory block according to a first test mode signal and a second test mode signal; and

a test pattern setup circuit configured to store a test pattern source signal in a feedback loop varied according to a third test mode signal and output the stored test pattern source signal as the first test pattern.

2. The semiconductor memory of claim 1, wherein the second test pattern includes a command signal input from a position outside of the semiconductor memory and an address signal corresponding to the command signal.

3. The semiconductor memory of claim 1, wherein the switching circuit includes:

a plurality of demultiplexers configured to output a command signal and an address signal as the test pattern source signal or the second test pattern according to the first test mode signal; and

a plurality of multiplexers configured to provide the first test pattern or the second test pattern to the memory block according to the second test mode signal.

4. The semiconductor memory of claim 3, wherein the plurality of demultiplexers are configured to provide the first test pattern or the second test pattern as an internal command signal and an internal address signal to the memory block.

5. The semiconductor memory of claim 1, wherein the test pattern setup circuit includes a plurality of programmable pipe latches.

6. The semiconductor memory of claim 5, wherein each of the plurality of programmable pipe latches includes:

a plurality of flip flops configured to sequentially shift input signals thereof to next-stage flip flops according to a clock signal; and

a plurality of multiplexers configured to output outputs of previous flip flops or a feedback output of a final flip flop among the plurality of flip flops according to signal bits of the third test mode signal.

19. The semiconductor memory of claim 1, wherein the memory block is configured to perform on operation according to a dummy test pattern or an external test pattern.

20. The semiconductor memory of claim 19, wherein the switching circuit is configured to provide the external test pattern or the dummy test pattern to the memory block.

21. The semiconductor memory of claim 1, wherein dummy test patterns of a plurality of channels have a same value or different values according to the third test mode signal.

7. A memory system comprising:

a plurality of channels,

wherein the memory system is configured to operate remaining channels according to a first test pattern other than one channel among the plurality of channels, and allow the one channel to perform a test operation according to a second test pattern.

8. The memory system of claim 7, wherein the plurality of channels are a plurality of semiconductor chips having individual input/output (I/O) terminals.

9. The memory system of claim 7, wherein the plurality of channels are simultaneously operated according to the first test pattern or the second test pattern.

10. The memory system of claim 7, wherein the remaining channels are configured to be operated according to the first test pattern having different values.

11. The memory system of claim 7, wherein the remaining channels are configured to perform a dummy operation in which no data I/O is performed through data I/O terminals thereof.

12. The memory system of claim 7, wherein the remaining channels are configured to repeatedly perform operation sections according to the first test pattern having different values based on a clock signal.

13. The memory system of claim 7, wherein each of the plurality of channels includes:

a memory block configured to perform an operation according to the first test pattern or the second test pattern;

a switching circuit configured to provide the first test pattern or the second test pattern to the memory block according to a first test mode signal and a second test mode signal; and

a test pattern setup circuit configured to store a test pattern source signal in a feedback loop varied according to a third test mode signal and output the stored test pattern source signal as the first test pattern.

14. The memory system of claim 13, wherein the second test pattern includes a command signal and an address signal which are currently input from an outside position of the memory system.

15. The memory system of claim 13, wherein the switching circuit includes:

a plurality of demultiplexers configured to output a command signal and an address signal as the test pattern source signal or the second test pattern according to the first test mode signal; and

a plurality of multiplexers configured to provide the first test pattern or the second test pattern to the memory block according to the second test mode signal.

16. The memory system of claim 15, wherein the plurality of demultiplexers are configured to provide the first test pattern or the second test pattern as an internal command signal and an internal address signal to the memory block.

17. The memory system of claim 13, wherein the test pattern setup circuit includes a plurality of programmable pipe latches.

18. The memory system of claim 17, wherein each of the plurality of programmable pipe latches includes:

a plurality of flip flops configured to sequentially shift input signals thereof to next-stage flip flops according to a clock signal; and

a plurality of multiplexers configured to output outputs of previous flip flops or a feedback output of a final flip flop among the plurality of flip flops according to signal bits of the third test mode signal.