Data encoding in solid-state storage apparatus

• US 9,502,138 B2
• Filed: 09/25/2014
• Issued: 11/22/2016
• Est. Priority Date: 11/28/2013
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Mittelholzer, Thomas, Papandreou, Nikolaos, Pozidis, Charalampos
• Primary Examiner(s): MCMAHON, DANIEL F
• Application Number:
  US14/496,416
• Publication Number:
  US 20150149872A1
• Time in Patent Office: 789 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: G06F 11/1068 in sector programmable memories, e.g. flash disk G06F11/1072 takes precedence
• CPC Class Codes: G06F 3/0619 in relation to data integrity, e.g. data losses, bit errors
• CPC Class Codes: G06F 3/064 Management of blocks
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G11C 29/52 Protection of memory contents; Detection of errors in memory contents
• CPC Class Codes: G11C 29/70 Masking faults in memories by using spares or by reconfiguring
• CPC Class Codes: H03M 13/13 Linear codes
• CPC Class Codes: H03M 13/152 Bose-Chaudhuri-Hocquenghem [BCH] codes
• CPC Class Codes: H03M 13/63 Joint error correction and other techniques H03M13/31 and H03M13/33 take precedence

Abstract

A method for encoding an input data block for storage in q-level cells of solid-state memory includes producing a preliminary block from the input data block by modulation encoding at least part of the input block into a first group of q^ary symbols via a first drift-tolerant encoding scheme, the preliminary block comprising the first group of q^ary symbols and any remainder of the input block not encoded via the first encoding scheme; generating parity data for the preliminary block via an error-correction encoding scheme; modulation encoding the parity data and any remainder of the input block into a second group of q^ary symbols via a second drift-tolerant encoding scheme; and supplying the q^ary symbols of the first and second groups for storage in respective q-level memory cells.

Claims

1. A method for encoding an input data block for storage in q-level cells of solid-state memory, the method comprising:

producing a preliminary block from the input data block by modulation encoding at least part of the input data block into a first group of q symbols via a first drift-tolerant encoding scheme, the preliminary block comprising the first group of q symbols and any remainder of the input data block not encoded via the first encoding scheme;

generating parity data for the preliminary block via an error-correction encoding scheme;

modulation encoding the parity data and any remainder of the input data block into a second group of q symbols via a second drift-tolerant encoding scheme; and

supplying the q symbols of the first group of q symbols and the second group of q symbols for storage in respective q-level memory cells, wherein q>

2.

2. The method of claim 1, wherein each of the first and second drift-tolerant encoding schemes comprises a permutation-based encoding scheme.

3. The method of claim 1, wherein the first drift-tolerant encoding scheme uses at least one drift-tolerant modulation code having a length of at least 28 q symbols.

4. The method of claim 2, wherein the first drift-tolerant encoding scheme uses a single permutation modulation code.

5. The method of claim 1, wherein the second drift-tolerant encoding scheme uses at least one drift-tolerant modulation code having a dimensionless rate of at least about 0.9.

6. The method of claim 1, wherein the second drift-tolerant encoding scheme is adapted to inhibit error propagation on decoding.

7. The method of claim 6, wherein the second drift-tolerant encoding scheme uses at least one single-parity-check code.

8. The method of claim 1, wherein the error-correction encoding scheme uses at least one BCH code.

9. A method for recording an input data block in q-level cells of solid-state memory, the method comprising:

encoding the input data block by producing a preliminary block from the input data block by modulation encoding at least part of the input data block into a first group of q symbols via a first drift-tolerant encoding scheme, the preliminary block comprising the first group of q symbols and any remainder of the input data block not encoded via the first encoding scheme, generating parity data for the preliminary block via an error-correction encoding scheme, modulation encoding the parity data and any remainder of the input data block into a second group of q symbols via a second drift-tolerant encoding scheme, and supplying the q symbols of the first and second groups for storage in respective q-level memory cells; and

storing the q symbols of the first group of q symbols and second group group of q symbols in respective q-level memory cells, wherein q>

2.

10. The method of claim 9, further comprising storing the first group of q symbols and the second group of q symbols in respective cells of a single solid-state memory array.

11. The method of claim 9, further comprising:

recording the input data block in q-level cells of p parallel solid-state memory arrays, wherein the p parallel memory arrays have respective associated first encoders, for implementing the first drift-tolerant encoding scheme, and respective associated second encoders, for collectively implementing the second drift-tolerant encoding scheme;

partitioning the at least part of the input data block into p first portions;

modulation encoding each first portion in a respective first encoder to produce a first set of q symbols, whereby the p first sets of q symbols collectively form the first group of q symbols;

partitioning the parity data and any remainder of the input data block into p second portions;

modulation encoding each second portion in a respective second encoder to produce a second set of q symbols, whereby the p second sets of q symbols collectively form the second group of q symbols; and

storing the first and second sets of q symbols output by the first encoder and the second encoder associated with q-level cells in each of the p parallel memory arrays.

12. The method of claim 9, further comprising:

reading memory cells storing the input block to obtain read signal components corresponding to respective q symbols of the first group of q symbols and the second group of q symbols;

processing the read signal components for the first group of q symbols in dependence on the first drift-tolerant encoding scheme to obtain statistical data for the distribution of the read signal components corresponding to each of the q memory cell levels;

detecting at least one codeword of the first drift-tolerant encoding scheme corresponding to the read signal components for the first group of q symbols;

using the statistical data to decode, in dependence on the second drift-tolerant encoding scheme, the parity data and any remainder of the input block from the read signal components for the second group of q symbols;

decoding, in dependence on the error-correction encoding scheme, the preliminary block from the at least one codeword of the first drift-tolerant encoding scheme, the parity data and any remainder of the input block; and

decoding the input data block from the preliminary block in dependence on the first drift-tolerant encoding scheme.

13. The method of claim 12, wherein the first drift-tolerant encoding scheme and second drift-tolerant encoding scheme are adapted such that a level error rate of the second drift-tolerant encoding scheme is within an order of magnitude of that of the first scheme.

14. An encoder apparatus for encoding an input data block for storage in q-level cells of solid-state memory, comprising:

a first drift-tolerant encoding stage for modulation encoding at least part of the input block into a first group of q symbols via a first drift-tolerant encoding scheme;

an error-correction encoder arranged for receiving a preliminary block, which comprises the first group of q symbols and any remainder of the input block not encoded by the first drift-tolerant encoding stage, and adapted to generate parity data for the preliminary block in accordance with an error-correction encoding scheme; and

a second drift-tolerant encoding stage for modulation encoding the parity data and any remainder of the input block into a second group of q symbols via a second drift-tolerant encoding scheme;

the apparatus being adapted to supply the q symbols of the first group of q symbols and the second group of q symbols for storage in respective q-level memory cells, wherein q>

2.

15. The encoder apparatus of claim 14, wherein each of the first and second drift-tolerant encoding schemes comprises a permutation-based encoding scheme.

16. The encoder apparatus of claim 14, wherein the first drift-tolerant encoding scheme uses at least one drift-tolerant modulation code having a length of at least 28 q symbols.

17. The encoder apparatus of claim 16, wherein the first drift-tolerant encoding scheme uses a single permutation modulation code.

18. The encoder apparatus of claim 14, wherein the second drift-tolerant encoding scheme uses at least one drift-tolerant modulation code having a dimensionless rate of at least about 0.9.