Vertical gate all around (VGAA) transistors and methods of forming the same

• US 9,502,265 B1
• Filed: 11/04/2015
• Issued: 11/22/2016
• Est. Priority Date: 11/04/2015
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chen, Shih-Chiang, Jiang, Ching-Hong, Wang, Li-Ting, Tsai, Teng-Chun
• Primary Examiner(s): Nhu, David
• Application Number:
  US14/932,777
• Time in Patent Office: 384 Days
• Field of Search: 438/692, 438/775, 438/740, 438/712, 438/311, 438/680, 438/679, 438/780, 438/770, 438/786, 438/791, 257/E21.006, 257/E21.007, 257/E21.041, 257/E21.126, 257/E21.127, 257/E21.157, 257/E21.17, 257/E21.218, 257/E21.304, 257/E21.229, 257/E21.267, 257/E21.278, 257/E21.293, 257/E21.32, 257/E21.441
• US Class Current: 1/1
• CPC Class Codes: H01L 21/31053 involving a dielectric removal step
• CPC Class Codes: H01L 21/31055 the removal being a chemical etching step, e.g. dry etching etching per se H01L21/311
• CPC Class Codes: H01L 21/31155 by ion implantation
• CPC Class Codes: H01L 29/0676 oriented perpendicular or at an angle to a substrate
• CPC Class Codes: H01L 29/42392 fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/4966 the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/66439 with a one- or zero-dimensional channel, e.g. quantum wire FET, in-plane gate transistor [IPG], single electron transistor [SET], striped channel transistor, Coulomb blockade transistor with an active layer made of a group 13/15 material H01L29/66469
• CPC Class Codes: H01L 29/66469 with one- or zero-dimensional channel, e.g. quantum wire field-effect transistors, in-plane gate transistors [IPG], single electron transistors [SET], Coulomb blockade transistors, striped channel transistors
• CPC Class Codes: H01L 29/775 with one dimensional charge carrier gas channel, e.g. quantum wire FET
• CPC Class Codes: H01L 29/78642 Vertical transistors

Abstract

An embodiment method includes forming a nanowire extending upwards from a substrate, wherein the nanowire includes: a bottom semiconductor region; a middle semiconductor region over the bottom semiconductor region; and a top semiconductor region over the middle semiconductor region. The method also includes forming a dielectric layer around and extending over the nanowire and forming a chemical mechanical polish-stop (CMP-stop) layer within the dielectric layer using an implantation process. After forming the CMP-stop layer, the dielectric layer is planarized.

Claims

1. A method of forming a vertical gate all around (VGAA) transistor, the method comprising:

forming a nanowire extending upwards from a substrate, wherein the nanowire comprises;

a bottom semiconductor region;

a middle semiconductor region over the bottom semiconductor region; and

a top semiconductor region over the middle semiconductor region;

forming a dielectric layer around and extending over the nanowire;

forming a chemical mechanical polish-stop (CMP-stop) layer within the dielectric layer using an implantation process, wherein the implantation process changes an etching rate of a portion of the dielectric layer; and

after forming the CMP-stop layer, planarizing the dielectric layer.

2. The method of claim 1, wherein the implantation process comprises implanting silicon, carbon, nitrogen, germanium, arsenic, argon, or a combination thereof in the dielectric layer.

3. The method of claim 2, wherein the implantation process comprises implanting silicon, carbon, nitrogen, germanium, arsenic, argon, or a combination thereof in the dielectric layer at a concentration of about 1×

10¹³ atoms/cm² to about 1×

10¹⁶ atoms/cm².

4. The method of claim 1, wherein the implantation process comprises controlling an implantation energy during the implantation process in accordance with a desired position and thickness of the CMP-stop layer within the dielectric layer.

5. The method of claim 4, wherein the implantation energy is about 0.1 KeV to about 350 KeV.

6. The method of claim 1 further comprising, prior to forming the CMP-stop layer, planarizing the dielectric layer.

7. The method of claim 1 further comprising after planarizing the dielectric layer, etching back the dielectric layer so that a top surface of the dielectric layer is substantially level with a top surface of the bottom semiconductor region or a top surface of the middle semiconductor region.

8. The method of claim 7, further comprising prior to etching back the dielectric layer, forming an etch-stop layer within the dielectric layer using an implantation process.

9. A method of forming a vertical gate all around (VGAA) transistor,

the method comprising:

forming a dielectric layer around and extending above a nanowire;

using a first implantation process to form a chemical mechanical polish-stop (CMP-stop) layer within the dielectric layer;

planarizing the dielectric layer to remove an upper portion of the dielectric layer over the CMP-stop layer;

using a second implantation process to form an etch-stop layer within the dielectric layer; and

applying an etching process so that a top surface of the dielectric layer is substantially level with a surface of at least one source/drain region of the nanowire.

10. The method of claim 9, wherein the second implantation process comprises decreasing an etching rate of an implanted portion of the dielectric layer during the etching process, wherein the implanted portion of the dielectric layer is the etch-stop layer.

11. The method of claim 10, wherein the second implantation process comprises implanting silicon, carbon, nitrogen, or a combination thereof in the implanted portion of the dielectric layer.

12. The method of claim 10, wherein after the second implantation process, an un-implanted portion of the dielectric layer is disposed over the etch-stop layer.

13. The method of claim 9, wherein the second implantation process comprises increasing an etching rate of an implanted portion the dielectric layer during the etching process, wherein an un-implanted portion of the dielectric layer is the etch-stop layer.

14. The method of claim 13, wherein the second implantation process comprises implanting argon, xenon, silicon, germanium, arsenic, phosphate, boron, or a combination thereof in the implanted portion of the dielectric layer.

15. The method of claim 9 further comprising planarizing the dielectric layer prior to forming the first implantation process.

16. A method of forming a vertical gate all around (VGAA) transistor, the method comprising:

forming a first dielectric layer over and extending along sidewalls of a nanowire, wherein the nanowire comprises;

a bottom source/drain region;

a channel region over the bottom source/drain region; and

a top source/drain region over the channel region;

implanting a first chemical mechanical polish-stop (CMP-stop) layer within the first dielectric layer;

after implanting the first CMP-stop layer, planarizing the first dielectric layer;

after planarizing the first dielectric layer, applying a first etching process so that a top surface of the first dielectric layer is substantially level with a top surface of the bottom source/drain region;

forming a gate structure around the channel region;

forming a second dielectric layer over the first dielectric layer and extending over the gate structure;

implanting a second CMP-stop layer within the second dielectric layer;

after implanting the second CMP-stop layer, planarizing the second dielectric layer; and

after planarizing the second dielectric layer, applying a second etching process so that a top surface of the second dielectric layer is substantially level with a top surface of the channel region.

17. The method of claim 16 further comprising prior to implanting the first CMP-stop layer, planarizing the first CMP-stop layer.

18. The method of claim 16 further comprising prior to the first etching process, implanting an etch-stop layer in the first dielectric layer, wherein the first etching process etches the first dielectric layer at a faster rate than the etch-stop layer.

19. The method of claim 16 further comprising prior to the first etching process, implanting an etching layer in the first dielectric layer, wherein the first etching process etches the first dielectric layer at a slower rate than the etching layer.

20. The method of claim 16 further comprising:

after the second etching process, removing a portion of the gate structure extending over the second dielectric layer to expose the top source/drain region;

forming a third dielectric layer around the top source/drain region;

forming a first source/drain contact extending through the third dielectric layer and electrically connected to the top source/drain region;

forming a gate contact extending through the second dielectric layer and the third dielectric layer and electrically connected to the gate structure; and

forming a second source/drain contact extending through the first dielectric layer, the second dielectric layer, and the third dielectric layer and electrically connected to the bottom source/drain region.