Method for manufacturing tested apparatus and method for manufacturing system including tested apparatus

• US 9,502,314 B2
• Filed: 07/29/2014
• Issued: 11/22/2016
• Est. Priority Date: 07/31/2013
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Takakura, Kazuya, Takahashi, Tetsuji, Ishikawa, Toru
• Primary Examiner(s): Perkins, Pamela E
• Application Number:
  US14/445,603
• Publication Number:
  US 20150037914A1
• Time in Patent Office: 847 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: G11C 2029/4402 Internal storage of test result, quality data, chip identification, repair information
• CPC Class Codes: G11C 29/006 at wafer scale level, i.e. wafer scale integration [WSI]
• CPC Class Codes: G11C 29/1201 comprising I/O circuitry
• CPC Class Codes: G11C 29/48 Arrangements in static stores specially adapted for testing by means external to the store, e.g. using direct memory access [DMA] or using auxiliary access paths
• CPC Class Codes: G11C 29/56008 Error analysis, representation of errors
• CPC Class Codes: G11C 29/832 with disconnection of faulty elements
• CPC Class Codes: H01L 22/14 for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06517 Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 2225/06596 Structural arrangements for testing testing or measuring during manufacture or treatment H01L22/00; testing electrical properties or locating electrical faults G01R31/00
• CPC Class Codes: H01L 24/94 at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 25/0652 the devices being arranged next and on each other, i.e. mixed assemblies
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 25/18 the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
• CPC Class Codes: H01L 25/50 Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA

Abstract

Disclosed herein is a method for manufacturing a tested apparatus that includes forming a stacked structure that includes a plurality of first semiconductor chips stacked over a semiconductor wafer. The semiconductor wafer comprises a plurality of second semiconductor chips that are arranged in matrix of a plurality of rows and columns. Each of the first semiconductor chips is stacked over and electrically connected to a different one of the second semiconductor chips. The method further includes contacting a probe card to at least one of the first semiconductor chips to perform a first test operation on a corresponding one of the second semiconductor chips with an intervention of the at least one of the first semiconductor chips so that a plurality of tested apparatus each comprising a pair of first and second semiconductor chips stacked with each other is derived.

Claims

1. A method for manufacturing a tested apparatus, the method comprising:

forming a stacked structure that includes a plurality of first semiconductor chips stacked over a semiconductor wafer, the semiconductor wafer comprising a plurality of second semiconductor chips that are arranged in matrix of a plurality of rows and columns, each of the first and second semiconductor chips includes a first conductive structure and a second conductive structure that is (1) electrically isolated from the first conductive structure and (2) staggered such that a portion of the second conductive structure overlaps the first conductive structure, the portion of the second conductive structure of each of the first semiconductor chips being stacked over and electrically connected to the first conductive structure of a different one of the second semiconductor chips;

contacting a probe card to at least one of the first semiconductor chips;

while contacting the probe card, performing a first test operation on the at least one of the first semiconductor chips via the first conductive structure of the at least one of the first semiconductor chips; and

while performing the first test operation, performing a second test operation independent of the first test operation on a corresponding one of the second semiconductor chips over which the at least one of the first semiconductor chips is stacked via the second conductive structure of the at least one of the first semiconductor chips.

2. The method as claimed in claim 1, wherein the contacting the probe card comprises contacting the probe card to the at least one of the first semiconductor chip to perform the first test operation on an internal circuit of the at least one of the first semiconductor chips.

3. The method as claimed in claim 2, wherein a period of time when the first test operation is performed on the corresponding one of the second semiconductor chip and a period of time when the first test operation is performed on the at least one of the first semiconductor chip, during the contacting, partly overlap with each other.

4. The method as claimed in claim 1, wherein the forming the stacked structure comprises:

providing an additional semiconductor wafer in which the first semiconductor chips are arranged in matrix of a plurality of rows and columns; and

dicing the additional semiconductor wafer to separate the first semiconductor chips from one another and stack the first semiconductor chips over the semiconductor wafer.

5. The method as claimed in claim 1, wherein the forming the stacked structure comprises:

providing an additional semiconductor wafer in which the first semiconductor chips are arranged in matrix of a plurality of rows and columns; and

stacking the additional semiconductor wafer over the semiconductor wafer to form the stacked structure.

6. The method as claimed in claim 1, wherein the forming the stacked structure comprises stacking a defective one of the first semiconductor chips over a defective one of the second semiconductor chips.

7. The method as claimed in claim 1, further comprising dicing at least semiconductor wafer to separate the tested apparatus from one another.

8. The method as claimed in claim 1, wherein each of the first semiconductor chips includes a first semiconductor substrate including a first surface over which a plurality of first circuits are formed and a second surface that is opposite to the first surface, each of the second semiconductor chips includes a second semiconductor substrate including a third surface over which a plurality of second circuits are formed and a fourth surface that is opposite to the third surface, and each of the first semiconductor chips is stacked over a corresponding one of the second semiconductor chips so that the second surface of the first semiconductor substrate faces to the third surface of the corresponding one of the second semiconductor chips.

9. The method as claimed in claim 8, wherein each of the first semiconductor chips includes a plurality of through substrate conductors penetrating through the first substrate of each of the first semiconductor chips.

10. The method as claimed in claim 1, further comprising determining that the corresponding one of the second semiconductor chips is defective based on the second test operation and subsequently deactivating the second semiconductor chip.

11. The method as claimed in claim 10 wherein deactivating the second semiconductor circuit includes programming an anti-fuse element of the corresponding one of the second semiconductor chips.

12. The method as claimed in claim 1 wherein the portion of the second conductive structure includes a wiring layer.

13. The method as claimed in claim 1 wherein the portion of the second conductive structure includes a through-hole conductor.

14. The method as claimed in claim 1 wherein the first conductive structure includes a surface bump, and wherein the portion of the second conductive structure include a through-hole conductor aligned with the surface bump.

15. The method as claimed in claim 1 wherein the first conductive structure includes a first surface bump, and wherein the portion of the second conductive structure includes a second surface bump aligned with the first surface bump.

16. The method as claimed in claim 1 wherein:

performing the first test operation includes performing the first test operation over a first period of time; and

performing the second operation includes performing the second test operation over a second period of time that overlaps the first period of time.

17. A method for manufacturing a tested apparatus, the method comprising:

stacking a first semiconductor chip over a second semiconductor chip that is arranged in a matrix with a plurality of other semiconductor chips in a semiconductor wafer, wherein the first and second semiconductor chips each include an internal circuit, a first conductive structure electrically coupled to the internal circuit, and a second conductive structure electrically isolated from the internal circuit, wherein the second conductive structure is staggered such that a portion of the second conductive structure extends beneath the first conductive structure;

coupling the portion of the second conductive structure of the first semiconductor chip to the first conductive structure of the second semiconductor chip;

performing a first electrical test of the internal circuit of the first semiconductor chip over a first period of time and via the first conductive structure of the first chip; and

performing a second electrical test of the internal circuit of the second semiconductor chip over a second period of time and via the second conductive structure of the first semiconductor chip, wherein the second period of time overlaps the first period of time, and wherein the second electrical test is performed separately from the first electrical test of the internal circuit of the first semiconductor chip.

18. The method as claimed in claim 17 wherein the second conductive structure of the second semiconductor chip is electrically isolated from the internal circuit of the first semiconductor chip.