Method of making a semiconductor device package with dummy gate

• US 9,502,334 B2
• Filed: 01/15/2016
• Issued: 11/22/2016
• Est. Priority Date: 10/21/2010
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Yang, Hsueh-An
• Primary Examiner(s): Dulka, John P
• Application Number:
  US14/996,979
• Publication Number:
  US 20160133546A1
• Time in Patent Office: 312 Days
• US Class Current: 1/1
• CPC Class Codes: B81B 7/008 MEMS characterised by an electronic circuit specially adapted for controlling or driving the same B81B7/0087 takes precedence; arrangements for starting, regulating, braking, or otherwise controlling an actuator H02N; control arrangements or circuits for visual indicators G09G3/00
• CPC Class Codes: B81C 1/0023 Packaging together an electronic processing unit die and a micromechanical structure die MEMS packages B81B7/0032; MEMS packaging processes B81C1/00261
• CPC Class Codes: B81C 1/00238 Joining a substrate with an electronic processing unit and a substrate with a micromechanical structure
• CPC Class Codes: B81C 1/00571 Avoid or control under-cutting
• CPC Class Codes: B81C 2203/0771 Stacking the electronic processing unit and the micromechanical structure
• CPC Class Codes: H01L 21/76 Making of isolation regions between components
• CPC Class Codes: H01L 21/76885 By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05 of an individual bonding area
• CPC Class Codes: H01L 2224/05552 in top view
• CPC Class Codes: H01L 2224/05569 the external layer being disposed on a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/13 of an individual bump connector
• CPC Class Codes: H01L 2224/13022 the bump connector being at least partially embedded in the surface
• CPC Class Codes: H01L 23/3171 the coating being directly applied to the semiconductor body, e.g. passivation layer H01L23/3178 takes precedence
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/53238 Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/1461 : MEMS

Abstract

A semiconductor device package includes a first substrate, which has a lower substrate surface and an upper substrate surface. A conductive dummy gate structure is disposed over the upper substrate surface. An interconnect structure is disposed over the conductive dummy gate structure. The interconnect structure includes a plurality of metal layers disposed within a dielectric structure and at least one of the metal layers is electrically coupled to the conductive dummy gate structure. A conductive through-substrate via extends from the lower substrate surface to an underside of the conductive dummy gate structure and is electrically coupled to the conductive dummy gate structure.

Claims

1. A semiconductor device package, comprising:

a first substrate including a lower substrate surface and an upper substrate surface;

a conductive dummy gate structure disposed over the upper substrate surface;

an interconnect structure disposed over the conductive dummy gate structure, wherein the interconnect structure includes a plurality of metal layers disposed within a dielectric structure and wherein at least one of the metal layers is electrically coupled to the conductive dummy gate structure; and

a conductive through-substrate via extending from the lower substrate surface to an underside of the conductive dummy gate structure and being electrically coupled to the conductive dummy gate structure, wherein the conductive dummy gate structure covers an entire uppermost surface of the conductive through-substrate via.

2. The semiconductor device package of claim 1, wherein the conductive through-substrate via makes direct contact with the underside of the conductive dummy gate structure.

3. The semiconductor device package of claim 1, wherein the conductive through-substrate via makes electrical connection with a lowermost of the plurality of metal layers through the conductive dummy gate structure and through one or more contact plugs extending between the conductive dummy gate structure and the lowermost of the plurality of metal layers.

4. The semiconductor device package of claim 3, wherein the conductive dummy gate structure is made of polysilicon.

5. The semiconductor device package of claim 1, wherein the conductive through-substrate via is disposed in a via opening and includes a conformal copper layer whose surface follows contours of the via opening without fully filling the via opening.

6. The semiconductor device package of claim 5, wherein the conductive through-substrate via includes a copper-barrier sub-layer and a copper-seed sub-layer.

7. The semiconductor device package of claim 5, further comprising:

a polymer layer filling a remainder of the via opening not filled by the conformal copper layer.

8. The semiconductor device package of claim 7, further comprising:

a dielectric material covering the lower substrate surface, wherein the via opening extends through the dielectric material and through the first substrate to establish via opening sidewalls; and

an isolation layer disposed over a lower surface of the dielectric material and extending along the via opening sidewalls but not covering the underside of the conductive dummy gate structure.

9. The semiconductor device package of claim 8, wherein the isolation layer is silicon dioxide, silicon nitride, or a combination of silicon dioxide and silicon nitride.

10. The semiconductor device package of claim 1, further comprising:

a second substrate disposed over the interconnect structure, wherein the second substrate includes one or more MEMS devices.

11. A semiconductor device package, comprising:

a first semiconductor substrate including a lower substrate surface and an upper substrate surface, wherein one or more CMOS devices are disposed on the first semiconductor substrate;

a conductive dummy gate structure disposed over the upper substrate surface;

an interconnect structure disposed over the conductive dummy gate structure, wherein the interconnect structure includes a plurality of metal layers disposed within a dielectric structure and wherein at least one of the metal layers is electrically coupled to the conductive dummy gate structure;

a second substrate disposed over the interconnect structure, wherein one or more MEMS devices are disposed on the second substrate and are coupled to the one or more CMOS devices through the interconnect structure;

a conductive through-substrate via extending from the lower substrate surface to an underside of the conductive dummy gate structure and being electrically coupled to the conductive dummy gate structure; and

one or more contact plugs arranged within a dielectric layer and extending between the conductive dummy gate structure and lower one of the plurality of metal layers that extends over the one or more contact plugs, wherein the one or more contact plugs and the dielectric layer completely separate the conductive through-substrate via from the lower one of the plurality of metal layers.

12. The semiconductor device package of claim 11, further comprising:

a gate dielectric disposed between the conductive dummy gate structure and the upper substrate surface.

13. The semiconductor device package of claim 12, wherein the conductive through-substrate via extends past innermost sidewalls of the gate dielectric to make direct contact with the underside of the conductive dummy gate structure.

14. The semiconductor device package of claim 11, further comprising:

a dielectric layer covering the lower substrate surface, wherein the via opening extends through the dielectric layer and through the first semiconductor substrate to establish a via opening having via opening sidewalls;

an isolation layer covering a lower surface of the dielectric layer and extending along the via opening sidewalls but not covering the underside of the conductive dummy gate structure;

a copper-barrier layer covering a lower surface of the isolation layer; and

a copper layer covering a lower surface of the copper-barrier layer and being separated from the isolation layer by the copper-barrier layer.

15. The semiconductor device package of claim 14, wherein the copper-barrier layer has a thickness ranging from 500 angstroms to 5000 angstroms.

16. The semiconductor device package of claim 14, wherein the copper layer has a thickness ranging from 2000 angstroms to 8000 angstroms.

17. The semiconductor device package of claim 14, wherein the copper-barrier layer comprises:

tantalum, titanium, tantalum nitride, or titanium nitride.

18. The semiconductor device package of claim 14:

wherein the copper layer is disposed in the via opening and is a conformal copper layer whose surface follows contours of the via opening without fully filling the via opening, and further comprising;

a polymer layer filling a remainder of the via opening not filled by the conformal copper layer.

19. A semiconductor device package, comprising:

a dielectric layer;

a semiconductor substrate including a lower substrate surface and an upper substrate surface, the lower substrate surface in direct contact with the dielectric layer;

a conductive dummy gate structure disposed over the upper substrate surface;

an interconnect structure disposed over the conductive dummy gate structure, wherein the interconnect structure includes a plurality of metal layers disposed within a dielectric structure and wherein at least one of the metal layers is electrically coupled to the conductive dummy gate structure;

a via opening having via opening sidewalls extending from a lower surface of the dielectric layer to an underside of the conductive dummy gate structure;

an isolation layer covering the lower surface of the dielectric layer and continuously extending along the via opening sidewalls to contact the underside of the conductive dummy gate structure but not to cover the underside of the conductive dummy gate structure;

a copper-barrier layer covering a lower surface of the isolation layer and contacting the underside of the conductive dummy gate structure; and

a copper layer covering a lower surface of the copper-barrier layer and being separated from the isolation layer by the copper-barrier layer.

20. The semiconductor device package of claim 19, wherein the conductive dummy gate structure covers an entire uppermost surface of the copper-barrier layer.