Semiconductor device and method of fabricating the same

• US 9,502,406 B1
• Filed: 08/28/2015
• Issued: 11/22/2016
• Est. Priority Date: 07/15/2014
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Park, Cheolwoo, Jung, Hyungsuk, Lee, Kwangyul, Lee, Jeongeon, Won, Seokjun
• Primary Examiner(s): Wilson, Allan R
• Application Number:
  US14/838,999
• Time in Patent Office: 452 Days
• Field of Search: 438/275
• US Class Current: 1/1
• CPC Class Codes: H01L 21/02063 the processing being the formation of vias or contact holes
• CPC Class Codes: H01L 21/28114 characterised by the sectional shape, e.g. T, inverted-T
• CPC Class Codes: H01L 21/31111 by chemical means
• CPC Class Codes: H01L 21/31116 by dry-etching
• CPC Class Codes: H01L 21/823456 gate conductors with different shapes, lengths or dimensions
• CPC Class Codes: H01L 21/823462 with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/495 the conductor material next to the insulator being a simple metal, e.g. W, Mo H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/4966 the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/6653 using the removal of at least part of spacer, e.g. disposable spacer
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66575 where the source and drain or source and drain extensions are self-aligned to the sides of the gate H01L29/66606 takes precedence

Abstract

Provided is a semiconductor device and method of fabricating the same. The device includes a substrate including a first region and a second region, a first gate pattern on the first region, a second gate pattern on the second region, and an interlayer insulating layer enclosing the first and second gate patterns. The first gate pattern including a first gate insulating layer and a first gate electrode, the second gate pattern including a second gate insulating layer and a second gate electrode, the first gate insulating layer is thicker than the second gate insulating layer, and a top width of the second gate pattern is larger than a bottom width thereof.

Claims

1. A semiconductor device, comprising:

a substrate including a first region and a second region;

a first trench and a second trench disposed on the first and second regions, respectively;

a first gate pattern provided in the first trench, the first gate pattern including a first gate insulating layer and a first gate electrode;

a second gate pattern provided in the second trench, the second gate pattern including a second gate insulating layer and a second gate electrode; and

an interlayer insulating layer enclosing the first and second gate patterns,

wherein the first gate insulating layer is thicker than the second gate insulating layer,

wherein the second trench has a width increasing in a direction away from the substrate, and

wherein a top entrance and a bottom surface of the first trench have substantially the same width.

2. The device of claim 1, wherein the first gate pattern is part of a high-voltage transistor formed on the first region, and the second gate pattern is part of a low-voltage transistor formed on the second region.

3. The device of claim 1, wherein the first and second gate electrodes have top surfaces that are coplanar with a top surface of the interlayer insulating layer.

4. The device of claim 1, wherein the first gate pattern further comprises a first high-k dielectric pattern and the second gate pattern further comprises a second high-k dielectric pattern.

5. The device of claim 4, wherein the first and second high-k dielectric patterns comprise at least one of hafnium oxide, hafnium silicon oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide, lead scandium tantalum oxide, or lead zinc niobate.

6. The device of claim 1, wherein the first and second gate electrodes comprises at least one of titanium, titanium nitride, tantalum, tantalum nitride, tungsten, copper, aluminum, or mixtures thereof.

7. The device of claim 1 wherein

top and bottom surfaces of the first gate pattern have substantially the same width, and

a top width of the second gate pattern is larger than a bottom width thereof.

13. The device of claim 8, the device of claim 1, wherein the first gate pattern further comprises a first high-k dielectric pattern and the second gate pattern further comprises a second high-k dielectric pattern.

14. The device of claim 13, wherein the first and second high-k dielectric patterns dispose on the sidewalls and bottom surfaces of the first and second gate electrodes, respectively.

8. A semiconductor device, comprising:

a substrate including a first region and a second region;

a first gate pattern on the first region, the first gate pattern including a first gate insulating layer and a first gate electrode;

a second gate pattern on the second region, the second gate pattern including a second gate insulating layer and a second gate electrode; and

spacers provided on sidewalls of each of the first and second gate patterns,

wherein a upper portion of each of the spacers of the first gate pattern has a width different from a upper portion of each of the spacers of the second gate pattern,

top and bottom surfaces of the first gate pattern have substantially the same width, and

a top width of the second gate pattern is larger than a bottom width thereof.

9. The device of claim 8, wherein a sidewall of the second gate pattern is tapered (inclined, slanted) compared to a sidewall of first gate pattern.

10. The device of claim 8, further comprising:

an interlayer insulating layer on the substrate, wherein

the first and second gate electrodes have top surfaces that are coplanar with a top surface of the interlayer insulating layer.

11. The device of claim 8, wherein the spacers comprise silicon nitride.

12. The device of claim 8, wherein the first and second gate electrodes comprise at least one of titanium, titanium nitride, tantalum, tantalum nitride, tungsten, copper, aluminum, or mixtures thereof.

15. The device of claim 8, wherein

the spacers on the sidewalls of the first gate pattern define a trench,

the first gate pattern is in the trench, and

a top and a bottom of the trench have substantially the same width.

16. A semiconductor device, comprising:

a substrate including a first region and a second region;

a first gate pattern on the first region, the first gate pattern including a first gate insulating layer and a first gate electrode;

a second gate pattern on the second region, the second gate pattern including a second gate insulating layer and a second gate electrode; and

an interlayer insulating layer enclosing the first and second gate patterns,

wherein the first gate insulating layer is thicker than the second gate insulating layer,

wherein the second gate pattern has a width increasing in a direction away from the substrate, and

wherein top and bottom surfaces of the first gate pattern have substantially the same width.

17. The device of claim 16, wherein the first and second gate electrodes comprise at least one of titanium, titanium nitride, tantalum, tantalum nitride, tungsten, copper, aluminum, or mixtures thereof.