Integrating a planar field effect transistor (FET) with a vertical FET

• US 9,502,407 B1
• Filed: 12/16/2015
• Issued: 11/22/2016
• Est. Priority Date: 12/16/2015
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Anderson, Brent A., Nowak, Edward J.
• Primary Examiner(s): Seven, Evren
• Application Number:
  US14/971,105
• Time in Patent Office: 342 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: H01L 21/265 producing ion implantation
• CPC Class Codes: H01L 21/28518 the conductive layers comprising silicides H01L21/28537 takes precedence
• CPC Class Codes: H01L 21/30604 Chemical etching
• CPC Class Codes: H01L 21/3085 characterised by their behaviour during the process, e.g. soluble masks, redeposited masks
• CPC Class Codes: H01L 21/76895 Local interconnects; Local pads, as exemplified by patent document EP0896365
• CPC Class Codes: H01L 21/823412 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823418 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823437 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 21/823456 gate conductors with different shapes, lengths or dimensions
• CPC Class Codes: H01L 21/823475 interconnection or wiring or contact manufacturing related aspects
• CPC Class Codes: H01L 21/823487 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823431
• CPC Class Codes: H01L 23/535 including internal interconnections, e.g. cross-under constructions internal lead connections H01L23/481
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 29/42392 fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H01L 29/78618 characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure silicide contacts, electrodes in general H01L29/458
• CPC Class Codes: H01L 29/78642 Vertical transistors
• CPC Class Codes: H01L 29/78696 : characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

One embodiment provides a method of integrating a planar field-effect transistor (FET) with a vertical FET. The method comprises masking and etching a semiconductor of the vertical FET to form a fin, and providing additional masking, additional etching, doping and depositions to isolate a bottom source/drain (S/D) region. A dielectric is formed on the bottom S/D region to form a spacer. The method further comprises depositing gate metals, etching a vertical gate for the vertical FET and a planar gate for the planar FET using a shared gate mask, depositing dielectric, etching the dielectric to expose one or more portions of the fin, growing epitaxy on a top S/D region, masking and etching S/D contact openings for the bottom S/D region, forming silicide regions in S/D regions, depositing contact metal in the silicide regions to form contacts, and planarizing the contacts.

Claims

1. A method of integrating a planar field-effect transistor (FET) with a vertical FET, comprising:

masking and etching a first semiconductor of the vertical FET to form a fin;

providing additional masking, additional etching, doping and depositions to isolate a bottom source/drain (S/D) region of the vertical FET;

depositing spacer dielectric on the bottom S/D region to form a spacer on the bottom S/D region;

etching back the fin to expose one or more vertical sections of the fin;

depositing gate metals on the first semiconductor and a second semiconductor of the planar FET;

etching a vertical gate for the vertical FET and a planar gate for the planar FET from the gate metals deposited using a shared gate mask, wherein the vertical gate is perpendicular to and extends across the first semiconductor, and the planar gate is perpendicular to and extends across the second semiconductor;

forming a gate dielectric isolating the second semiconductor from the planar gate by removing a portion of spacer and replacing the portion of the spacer removed with a high voltage gate dielectric layer;

depositing dielectric on the fin;

etching the dielectric deposited on the fin to expose one or more portions of the fin;

growing epitaxy on the one or more exposed portions of the fin;

masking and etching contact openings for contacts of the vertical FET and the planar FET;

forming silicide regions in S/D regions of the vertical FET and source and drain regions of the planar FET;

depositing contact metal in the silicide regions to form the contacts of the vertical FET and the planar FET; and

planarizing the contacts of the vertical FET and the planar FET.

2. The method of claim 1, further comprising:

isolating the bottom S/D region using one or more implants.

3. The method of claim 1, wherein:

removing a portion of spacer comprises removing a portion of the spacer in a planar region; and

the high voltage gate dielectric layer is a separate, planar-specific gate dielectric for the planar region.

4. The method of claim 1, wherein etching the dielectric deposited on the fin to expose one or more portions of the fin comprises exposing a top of the fin.

5. The method of claim 1, wherein growing epitaxy on the one or more exposed portions of the fin comprises growing epitaxy on a top S/D region of the vertical FET, and the fin connects the epitaxy in the top S/D region to the bottom S/D region.

6. The method of claim 1, further comprising:

forming the spacer using a reactive ion etching (RIE) process, wherein a gate contact for the vertical gate is masked using the shared gate mask during the RIE process.

7. The method of claim 1, wherein the vertical FET and the planar FET share the silicide regions and the contacts.

8. The method of claim 1, further comprising:

implanting the bottom S/D region in a vertical region and a planar region, such that the planar region and the vertical region share the bottom S/D region.

9. The method of claim 1, wherein a top of the vertical gate and a top of the planar gate are co-planar.

10. The method of claim 1, wherein the bottom S/D region is co-planar with an active region of the planar FET.