FinFET device including fins having a smaller thickness in a channel region, and a method of manufacturing same

• US 9,502,408 B2
• Filed: 11/14/2013
• Issued: 11/22/2016
• Est. Priority Date: 11/14/2013
• Status: Expired due to Fees

• Current Assignee: Alsephina Innovations Inc. (Quarterhill Inc. (f/k/a Wi-LAN Inc.))
• Original Assignee: GlobalFoundries, Inc.
• Inventors: Kerber, Pranita, Ouyang, Qiqing C., Reznicek, Alexander
• Primary Examiner(s): Stark, Jarrett
• Assistant Examiner(s): DINKE, BITEW A
• Application Number:
  US14/079,733
• Publication Number:
  US 20150129982A1
• Time in Patent Office: 1,104 Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/0886 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A method for manufacturing a fin field-effect transistor (FinFET) device, comprises forming a plurality of fins on a substrate to a first thickness, forming a sacrificial gate stack on portions of the fins, forming source drain junctions using ion implantation, forming a dielectric layer on the substrate, removing the sacrificial gate stack to expose the portions of the fins, thinning the exposed portions of the fins to a second thickness less than the first thickness, and forming a gate stack on the thinned exposed portions of the fins to replace the removed sacrificial gate stack.

Claims

1. A method for manufacturing a fin field-effect transistor (FinFET) device, the method comprising:

forming a plurality of fins on a substrate by patterning a semiconductor layer to a first thickness and a first height;

forming a sacrificial gate stack on portions of the fins in a channel region of the FinFET device;

forming source drain junctions in a source drain region of the FinFET device using ion implantation;

forming a dielectric layer on the substrate;

removing the sacrificial gate stack to expose the portions of the fins in the channel region, wherein the dielectric layer covers remaining portions of the fins in the source drain region;

thinning the exposed portions of the fins to a second thickness less than the first thickness, and reducing the exposed portions of the fins to a second height less than the first height, wherein the thinning removes about 50% to about 60% of the first thickness, and wherein each of a resulting height and thickness of the remaining portions of the fins in the source drain region is greater than each of a resulting height and thickness of the portions of the fins in the channel region such that an entirety of the patterned semiconductor layer comprising the fins in the source drain region are at the first height and the first thickness achieved prior to the thinning and reducing;

forming a gate stack on the thinned and reduced exposed portions of the fins to replace the removed sacrificial gate stack;

etching a plurality of contact holes in the dielectric layer; and

filling the contact holes with a conductive material to form contact bars extending across the plurality of fins;

wherein the contact bars couple respective portions of the plurality of fins together without epitaxial regions to merge adjacent fins.

2. The method according to claim 1, further comprising forming at least one spacer on the sacrificial gate stack.

3. The method according to claim 1, wherein the sacrificial gate stack is not formed on the remaining portions of the fins and the remaining portions of the fins remain at the first thickness.

4. The method according to claim 1, wherein the thinning of the exposed portions of the fins is performed by etching the exposed portions of the fins to remove about 50% to about 60% of the first thickness.

5. The method according to claim 4, wherein the etching of the exposed portions of the fins is performed with an etchant having a high selectivity with respect to a material of the fins.

6. The method according to claim 1, wherein removing the sacrificial gate stack leaves a cavity in the dielectric layer.

7. The method according to claim 1, wherein the second thickness is equal to about 50% of the first thickness.

8. The method according to claim 1, wherein the method prevents etching of the remaining portions of the fins in the source drain region to maintain the resulting height and thickness of the remaining portions of the fins in the source drain region at the first height and the first thickness.

9. A method for manufacturing a fin field-effect transistor (FinFET) device, the method comprising:

forming a plurality of fins on a substrate to a first thickness and a first height;

forming a sacrificial gate stack on portions of the fins in a channel region of the FinFET device;

forming source drain junctions in a source drain region of the FinFET device using ion implantation;

forming a dielectric layer on the substrate;

removing the sacrificial gate stack to expose the portions of the fins in the channel region, wherein the dielectric layer covers remaining portions of the fins in the source drain region;

thinning the exposed portions of the fins to a second thickness less than the first thickness, and reducing the exposed portions of the fins to a second height less than the first height, wherein the thinning removes about 50% to about 60% of the first thickness, and wherein each of a resulting height and thickness of the remaining portions of the fins in the source drain region is greater than each of a resulting height and thickness of the portions of the fins in the channel region;

forming a gate stack on the thinned and reduced exposed portions of the fins to replace the removed sacrificial gate stack;

etching a plurality of contact holes in the dielectric layer; and

filling the contact holes with a conductive material to form contact bars extending across the plurality of fins;

wherein the contact bars couple respective portions of the plurality of fins together without epitaxial regions to merge adjacent fins.

10. A method for manufacturing a fin field-effect transistor (FinFET) device, the method comprising:

forming a plurality of fins on a substrate to a first thickness and a first height;

forming a sacrificial gate stack on portions of the fins in a channel region of the FinFET device;

forming source drain junctions in a source drain region of the FinFET device using ion implantation;

forming a dielectric layer on the substrate;

removing the sacrificial gate stack to expose the portions of the fins in the channel region, wherein the dielectric layer covers remaining portions of the fins in the source drain region;

thinning the exposed portions of the fins to a second thickness less than the first thickness, and reducing the exposed portions of the fins to a second height less than the first height, wherein the thinning removes about 50% to about 60% of the first thickness, and wherein each of a resulting height and thickness of the remaining portions of the fins in the source drain region is greater than each of a resulting height and thickness of the portions of the fins in the channel region; and

forming a gate stack on the thinned and reduced exposed portions of the fins to replace the removed sacrificial gate stack.