Strained finFET device fabrication

• US 9,502,411 B1
• Filed: 08/24/2015
• Issued: 11/22/2016
• Est. Priority Date: 08/20/2015
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Doris, Bruce B., He, Hong, Kanakasabapathy, Sivananda K., Karve, Gauri, Lie, Fee Li, Sieg, Stuart A.
• Primary Examiner(s): Fan, Michele
• Application Number:
  US14/833,363
• Time in Patent Office: 456 Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02592 amorphous
• CPC Class Codes: H01L 21/26506 in group IV semiconductors
• CPC Class Codes: H01L 21/30604 Chemical etching
• CPC Class Codes: H01L 21/76213 introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose
• CPC Class Codes: H01L 21/823412 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823481 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 21/845 including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/0886 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/1211 combined with field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/16 including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
• CPC Class Codes: H01L 29/161 including two or more of the elements provided for in group H01L29/16 , e.g. alloys H01L29/1604 takes precedence
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/6653 using the removal of at least part of spacer, e.g. disposable spacer
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7846 the means being located in the lateral device isolation region, e.g. STI
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain
• CPC Class Codes: H01L 29/785 : having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7851 : with the body tied to the substrate

Abstract

A method for forming a fin on a substrate comprises patterning and etching a layer of a first semiconductor material to define a strained fin, depositing a layer of a second semiconductor material over the fin, the second semiconductor material operative to maintain the a strain in the strained fin, etching to remove a portion of the second semiconductor material to define a cavity that exposes a portion of the fin, etching to remove the exposed portion of the fin such that the fin is divided into a first segment and a second segment, and depositing an insulator material in the cavity, the insulator material contacting the first segment of the fin and the second segment of the fin.

Claims

1. A field effect transistor device comprising:

a first semiconductor fin having a profile with a horizontal length and a width where a dimension of the horizontal length is greater than a dimension of the width, the first semiconductor fin having a first distal end and a second distal end arranged on a substrate;

a second semiconductor fin having a profile with a horizontal length and a width where a dimension of the horizontal length is greater than a dimension of the width, the second semiconductor fin having a first distal end and a second distal end arranged on the substrate;

the second semiconductor fin and the first semiconductor fin arranged such that common longitudinal axis extends along the horizontal length of the first semiconductor fin and the horizontal length of the second semiconductor fin and passes through the first distal end and the second distal end of the first semiconductor fin and passes through the first distal end and the second distal end of the second semiconductor fin;

an insulator material disposed between and in contact with the first distal end of the first semiconductor fin and the first distal end of the second semiconductor fin such that the first distal end of the first semiconductor fin and the first distal end of the second semiconductor fin exert a compressive force on the insulator material; and

a first gate stack arranged over the first semiconductor fin.

2. The device of claim 1, further comprising a second gate stack arranged over the second semiconductor fin.

3. The device of claim 1, wherein the insulator material includes an oxide material.

4. The device of claim 1, wherein the insulator material includes a compressive oxide material.

5. The device of claim 1, wherein the first semiconductor fin includes a silicon germanium material and the second semiconductor fin includes a silicon germanium material.

6. The device of claim 1, wherein the first semiconductor fin includes a silicon germanium material and the second semiconductor fin includes a silicon material.

7. The device of claim 1, wherein the first semiconductor fin and the second semiconductor fin are arranged on an insulator layer.