Method and structure of making enhanced UTBB FDSOI devices
First Claim
1. An integrated circuit die, comprising:
- a first layer of semiconductor material;
a first layer of dielectric material positioned on the first layer of semiconductor material;
a second layer of semiconductor material positioned on the first layer of dielectric material, the second layer having a top surface, side surfaces, and a bottom surface, a central portion of the bottom surface being supported by the first layer of dielectric material, an exterior portion of the bottom surface being spaced from a top surface of the first layer of dielectric material by a distance; and
a transistor including;
a channel region in the second layer of semiconductor material;
a gate dielectric positioned on the top surface, the side surfaces, and on the portion of the bottom surface of the second layer of semiconductor material; and
a gate electrode positioned on the gate dielectric on the top surface, the side surfaces, and on the portion of the bottom surface of the second layer of semiconductor material.
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Accused Products
Abstract
An integrated circuit die includes a substrate having a first layer of semiconductor material, a layer of dielectric material on the first layer of semiconductor material, and a second layer of semiconductor material on the layer of dielectric material. An extended channel region of a transistor is positioned in the second layer of semiconductor material, interacting with a top surface, side surfaces, and potentially portions of a bottom surface of the second layer of semiconductor material. A gate dielectric is positioned on a top surface and on the exposed side surface of the second layer of semiconductor material. A gate electrode is positioned on the top surface and the exposed side surface of the second layer of semiconductor material.
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Citations
20 Claims
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1. An integrated circuit die, comprising:
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a first layer of semiconductor material; a first layer of dielectric material positioned on the first layer of semiconductor material; a second layer of semiconductor material positioned on the first layer of dielectric material, the second layer having a top surface, side surfaces, and a bottom surface, a central portion of the bottom surface being supported by the first layer of dielectric material, an exterior portion of the bottom surface being spaced from a top surface of the first layer of dielectric material by a distance; and a transistor including; a channel region in the second layer of semiconductor material; a gate dielectric positioned on the top surface, the side surfaces, and on the portion of the bottom surface of the second layer of semiconductor material; and a gate electrode positioned on the gate dielectric on the top surface, the side surfaces, and on the portion of the bottom surface of the second layer of semiconductor material. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. An integrated circuit die, comprising:
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a transistor structure that includes; a dielectric layer having a surface with a central area and an outer area; a first layer of semiconductor material, the first layer of semiconductor material including a top surface, side surfaces, and a bottom surface, a first portion of the bottom surface being on the central area of the surface of the dielectric layer and a second portion of the bottom surface being spaced from the outer area by a distance; a gate dielectric positioned on the top surface, on the second portion of the bottom surface, and on the side surfaces of the first layer of semiconductor material; a gate electrode positioned on the gate dielectric on the top surface, on the portion of the bottom surface, and on the side surfaces of the first layer of semiconductor material, a portion of the gate electrode being between the dielectric layer and the second portion of the bottom surface of the first layer of semiconductor material; a source region of the transistor is adjacent to the gate electrode; and a drain region of the transistor is adjacent to the gate electrode. - View Dependent Claims (11, 12, 13, 14)
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15. A device, comprising:
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a buried oxide layer having a surface where the surface has a first portion and a second portion; a first semiconductor region having a central portion and outer portions, the central portion being on the second portion of the buried oxide layer, the first portion of the buried oxide layer being separated from the outer portions of the first semiconductor region by a first space; and a gate electrode positioned on the first semiconductor region, on the buried oxide layer, and in the first space. - View Dependent Claims (16, 17, 18, 19, 20)
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Specification