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Method and structure of making enhanced UTBB FDSOI devices

  • US 9,502,505 B2
  • Filed: 12/31/2014
  • Issued: 11/22/2016
  • Est. Priority Date: 12/31/2014
  • Status: Active Grant
First Claim
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1. An integrated circuit die, comprising:

  • a first layer of semiconductor material;

    a first layer of dielectric material positioned on the first layer of semiconductor material;

    a second layer of semiconductor material positioned on the first layer of dielectric material, the second layer having a top surface, side surfaces, and a bottom surface, a central portion of the bottom surface being supported by the first layer of dielectric material, an exterior portion of the bottom surface being spaced from a top surface of the first layer of dielectric material by a distance; and

    a transistor including;

    a channel region in the second layer of semiconductor material;

    a gate dielectric positioned on the top surface, the side surfaces, and on the portion of the bottom surface of the second layer of semiconductor material; and

    a gate electrode positioned on the gate dielectric on the top surface, the side surfaces, and on the portion of the bottom surface of the second layer of semiconductor material.

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