Method and structure of making enhanced UTBB FDSOI devices

• US 9,502,505 B2
• Filed: 12/31/2014
• Issued: 11/22/2016
• Est. Priority Date: 12/31/2014
• Status: Active Grant

• Current Assignee: Stmicroelectronics Crolles 2 SAS (STMicroelectronics NV), STMicroelectronics Incorporated (STMicroelectronics NV)
• Original Assignee: Stmicroelectronics Crolles 2 SAS (STMicroelectronics NV), STMicroelectronics Incorporated (STMicroelectronics NV)
• Inventors: Liu, Qing, Skotnicki, Thomas
• Primary Examiner(s): MOORE, WHITNEY
• Application Number:
  US14/587,849
• Publication Number:
  US 20160190315A1
• Time in Patent Office: 692 Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/28114 characterised by the sectional shape, e.g. T, inverted-T
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/1033 with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with channel and gate aligned in the lengthwise direction H01L29/42376; with buried channel H01L29/7838
• CPC Class Codes: H01L 29/42356 Disposition, e.g. buried gate electrode H01L29/42324 and H01L29/4234 take precedence
• CPC Class Codes: H01L 29/66477 with an insulated gate, i.e. MISFET
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66575 where the source and drain or source and drain extensions are self-aligned to the sides of the gate H01L29/66606 takes precedence
• CPC Class Codes: H01L 29/66628 recessing the gate by forming single crystalline semiconductor material at the source or drain location
• CPC Class Codes: H01L 29/66651 with a single crystalline channel formed on the silicon substrate after insulating device isolation
• CPC Class Codes: H01L 29/7834 with a non-planar structure, e.g. the gate or the source or the drain being non-planar
• CPC Class Codes: H01L 29/7838 without inversion channel, e.g. buried channel lateral MISFETs, normally-on lateral MISFETs, depletion-mode lateral MISFETs

Abstract

An integrated circuit die includes a substrate having a first layer of semiconductor material, a layer of dielectric material on the first layer of semiconductor material, and a second layer of semiconductor material on the layer of dielectric material. An extended channel region of a transistor is positioned in the second layer of semiconductor material, interacting with a top surface, side surfaces, and potentially portions of a bottom surface of the second layer of semiconductor material. A gate dielectric is positioned on a top surface and on the exposed side surface of the second layer of semiconductor material. A gate electrode is positioned on the top surface and the exposed side surface of the second layer of semiconductor material.

Claims

1. An integrated circuit die, comprising:

a first layer of semiconductor material;

a first layer of dielectric material positioned on the first layer of semiconductor material;

a second layer of semiconductor material positioned on the first layer of dielectric material, the second layer having a top surface, side surfaces, and a bottom surface, a central portion of the bottom surface being supported by the first layer of dielectric material, an exterior portion of the bottom surface being spaced from a top surface of the first layer of dielectric material by a distance; and

a transistor including;

a channel region in the second layer of semiconductor material;

a gate dielectric positioned on the top surface, the side surfaces, and on the portion of the bottom surface of the second layer of semiconductor material; and

a gate electrode positioned on the gate dielectric on the top surface, the side surfaces, and on the portion of the bottom surface of the second layer of semiconductor material.

2. The integrated circuit die of claim 1, comprising a recess in the first layer of dielectric material below the portion of the bottom surface of the second layer of semiconductor material, the gate dielectric being positioned on all surfaces of the recess.

3. The integrated circuit die of claim 2 wherein the gate electrode includes a portion that extends into the recess and is on the gate dielectric below the bottom surface of the second layer of semiconductor material.

4. The integrated circuit die of claim 3 wherein a total channel width of the transistor includes a height of the second layer of semiconductor material, a width of the top surface, and a width of the portion of the bottom surface above the recess.

5. The integrated circuit die of claim 1 wherein the gate dielectric is further positioned on a portion of the first layer of dielectric material that is below the portion of the bottom surface.

6. The integrated circuit die of claim 1 wherein the transistor comprises a source region and a drain region positioned on the second layer of semiconductor material.

7. The integrated circuit die of claim 1 wherein the second layer of semiconductor material has a height less than 10 nm.

8. The integrated circuit die of claim 1 wherein the gate dielectric is a high K gate dielectric including hafnium or zirconium.

9. The integrated circuit die of claim 1, wherein the first layer of semiconductor material is a back gate.

10. An integrated circuit die, comprising:

a transistor structure that includes;

a dielectric layer having a surface with a central area and an outer area;

a first layer of semiconductor material, the first layer of semiconductor material including a top surface, side surfaces, and a bottom surface, a first portion of the bottom surface being on the central area of the surface of the dielectric layer and a second portion of the bottom surface being spaced from the outer area by a distance;

a gate dielectric positioned on the top surface, on the second portion of the bottom surface, and on the side surfaces of the first layer of semiconductor material;

a gate electrode positioned on the gate dielectric on the top surface, on the portion of the bottom surface, and on the side surfaces of the first layer of semiconductor material, a portion of the gate electrode being between the dielectric layer and the second portion of the bottom surface of the first layer of semiconductor material;

a source region of the transistor is adjacent to the gate electrode; and

a drain region of the transistor is adjacent to the gate electrode.

11. The integrated circuit die of claim 10, comprising a first layer of dielectric material, the first layer of semiconductor material being positioned directly on the first layer of dielectric material.

12. The integrated circuit die of claim 11 wherein the first layer of dielectric material is recessed from the portion of the bottom surface of the first layer of semiconductor material.

13. The integrated circuit die of claim 10 wherein the top surface of the first layer of semiconductor material has a first width, each of the side surfaces has a first height, and the portion of the bottom surface has a second width.

14. The integrated circuit die of claim 13 wherein a total width of a channel formed in the first layer of semiconductor material including the first width, the first height for a first one of the sides, the first height for a second one of the sides, and the second width.

15. A device, comprising:

a buried oxide layer having a surface where the surface has a first portion and a second portion;

a first semiconductor region having a central portion and outer portions, the central portion being on the second portion of the buried oxide layer, the first portion of the buried oxide layer being separated from the outer portions of the first semiconductor region by a first space; and

a gate electrode positioned on the first semiconductor region, on the buried oxide layer, and in the first space.

16. The device of claim 15, further comprising a gate dielectric between the gate electrode and the first semiconductor region.

17. The device of claim 15 wherein the gate electrode includes a liner formed on the first semiconductor region, the buried oxide layer, and in the first space and a conductive material formed on the liner.

18. The device of claim 17 wherein a portion of the conductive material is in the space between a first portion of the liner and a second portion of the liner.

19. The device of claim 15 wherein the first semiconductor region includes a top surface, side surfaces, and a bottom surface and the gate electrode is on the top surface, the side surfaces, and a portion of the bottom surface.

20. The device of claim 15 wherein a second portion of the buried oxide layer is separated from the first semiconductor region by a second space, the gate electrode being positioned in the second space.