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Stress relieving semiconductor layer

  • US 9,502,509 B2
  • Filed: 03/29/2016
  • Issued: 11/22/2016
  • Est. Priority Date: 05/01/2013
  • Status: Active Grant
First Claim
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1. A device comprising:

  • an active region;

    a p-type contact layer located on a first side of the active region; and

    a n-type contact layer located on a second side of the active region opposite the first side, wherein the n-type contact layer is located between the active region and a semiconductor structure comprising;

    a cavity containing layer, wherein the cavity containing layer is formed of a semiconductor material, has a thickness greater than two monolayers, and has a plurality of cavities, and wherein the plurality of cavities have a characteristic size of at least one nanometer and a characteristic separation of at least five nanometers.

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