Stress relieving semiconductor layer

• US 9,502,509 B2
• Filed: 03/29/2016
• Issued: 11/22/2016
• Est. Priority Date: 05/01/2013
• Status: Active Grant

• Current Assignee: Sensor Electronic Technology Incorporated (Seoul Semiconductor Co., Ltd.)
• Original Assignee: Sensor Electronic Technology Incorporated (Seoul Semiconductor Co., Ltd.)
• Inventors: Shatalov, Maxim S., Yang, Jinwei, Sun, Wenhong, Jain, Rakesh, Shur, Michael, Gaska, Remigijus
• Primary Examiner(s): Mandala, Victor A
• Application Number:
  US15/083,423
• Publication Number:
  US 20160211331A1
• Time in Patent Office: 238 Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/0237 Materials
• CPC Class Codes: H01L 21/02458 Nitrides
• CPC Class Codes: H01L 21/02505 consisting of more than two layers
• CPC Class Codes: H01L 21/02507 Alternating layers, e.g. superlattice
• CPC Class Codes: H01L 21/02513 Microstructure
• CPC Class Codes: H01L 21/0254 Nitrides
• CPC Class Codes: H01L 21/0262 Reduction or decomposition of gaseous compounds, e.g. CVD
• CPC Class Codes: H01L 21/02639 Preparation of substrate for selective deposition
• CPC Class Codes: H01L 21/0265 Pendeoepitaxy
• CPC Class Codes: H01L 29/0657 characterised by the shape of the body
• CPC Class Codes: H01L 29/158 Structures without potential periodicity in a direction perpendicular to a major surface of the substrate, i.e. vertical direction, e.g. lateral superlattices, lateral surface superlattices [LSS]
• CPC Class Codes: H01L 29/2003 Nitride compounds
• CPC Class Codes: H01L 29/205 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 33/007 comprising nitride compounds
• CPC Class Codes: H01L 33/12 with a stress relaxation structure, e.g. buffer layer

Abstract

A semiconductor structure, such as a group III nitride-based semiconductor structure is provided. The semiconductor structure includes a cavity containing semiconductor layer. The cavity containing semiconductor layer can have a thickness greater than two monolayers and a multiple cavities. The cavities can have a characteristic size of at least one nanometer and a characteristic separation of at least five nanometers.

Claims

1. A device comprising:

an active region;

a p-type contact layer located on a first side of the active region; and

a n-type contact layer located on a second side of the active region opposite the first side, wherein the n-type contact layer is located between the active region and a semiconductor structure comprising;

a cavity containing layer, wherein the cavity containing layer is formed of a semiconductor material, has a thickness greater than two monolayers, and has a plurality of cavities, and wherein the plurality of cavities have a characteristic size of at least one nanometer and a characteristic separation of at least five nanometers.

2. The device of claim 1, wherein the semiconductor structure further comprises:

a substrate;

a nucleation layer located on the substrate, wherein the nucleation layer has a thickness of at least one nanometer and contains no large scale cavities, and wherein the cavity containing layer is located directly on the nucleation layer; and

a semiconductor layer located directly on the cavity containing layer.

3. The device of claim 2, wherein the semiconductor layer is an AlN layer having a thickness between approximately 1 micron and approximately 4 microns.

4. The device of claim 2, wherein the semiconductor layer contains no large scale cavities.

5. The device of claim 2, wherein the cavity containing layer and the semiconductor layer are part of a superlattice of semiconductor layers including a plurality of cavity containing layers interchanged with a plurality of semiconductor layers.

6. The device of claim 5, wherein a bandgap for each semiconductor layer in the plurality of semiconductor layers differs from an adjacent semiconductor layer by at least two percent.

7. The device of claim 5, wherein the plurality of semiconductor layers in the superlattice of semiconductor layers have alternating tensile and compressive stresses.

8. The device of claim 1, wherein the device is configured to operate as one of:

a laser diode, a light emitting diode, a photodiode, a deep ultraviolet light emitting diode, a high mobility electron transistor, a field effect transistor, a p-n diode, or a Schottky diode.

9. The device of claim 1, wherein the cavity containing layer has a thickness between approximately one micron and approximately ten microns.

10. A device comprising:

an active region;

a p-type contact layer located on a first side of the active region; and

a n-type contact layer located on a second side of the active region opposite the first side, wherein the n-type contact layer is located between the active region and a semiconductor structure comprising;

a superlattice of semiconductor layers comprising;

a plurality of cavity containing layers alternating with a plurality of semiconductor layers, wherein each cavity containing layer is formed of a semiconductor material, has a thickness greater than two monolayers, and has a plurality of cavities, and wherein the plurality of cavities have a characteristic size of at least one nanometer and a characteristic separation of at least five nanometers, and wherein each semiconductor layer contains no cavities.

11. The device of claim 10, wherein at least one of:

the plurality of cavity containing layers or the plurality of semiconductor layers, have compositions that differ by at least one percent.

12. The device of claim 11, wherein an average molar fraction of aluminum in the at least one of:

the plurality of cavity containing layers or the plurality of semiconductor layers, is between 1 and a molar fraction of the n-type contact layer.

13. The device of claim 10, wherein at least one layer in at least one of:

the plurality of cavity containing layers or the plurality of semiconductor layers has a graded composition.

14. The device of claim 13, wherein a molar fraction of an element in the at least one layer differs by at least one percent from a first side of the at least one layer to an opposing side of the at least one layer.

15. The device of claim 10, wherein at least one of:

the characteristic size or the characteristic separation, of the plurality of cavities in a first cavity containing layer differs from the characteristic size or the characteristic separation of the plurality of cavities in a second cavity containing layer by at least one percent.

16. The device of claim 10, wherein the plurality of semiconductor layers in the superlattice of semiconductor layers have alternating tensile and compressive stresses.

17. The device of claim 10, wherein the device is configured to operate as one of:

a laser diode, a light emitting diode, a photodiode, a deep ultraviolet light emitting diode, a high mobility electron transistor, a field effect transistor, a p-n diode, or a Schottky diode.

18. A structure comprising:

a superlattice of semiconductor layers comprising;

a plurality of cavity containing layers alternating with a plurality of semiconductor layers, wherein each cavity containing layer is formed of a semiconductor material, has a thickness greater than two monolayers, and has a plurality of cavities, and wherein the plurality of cavities have a characteristic size of at least one nanometer and a characteristic separation of at least five nanometers, and wherein each semiconductor layer contains no cavities.

19. The structure of claim 18, wherein at least one of:

the plurality of cavity containing layers or the plurality of semiconductor layers have compositions that differ by at least one percent.

20. The structure of claim 18, wherein at least one layer in at least one of:

the plurality of cavity containing layers or the plurality of semiconductor layers has a graded composition.