Recessed access devices and gate electrodes

• US 9,502,516 B2
• Filed: 04/08/2014
• Issued: 11/22/2016
• Est. Priority Date: 05/11/2006
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Gibbons, Jasper S., Young, Darren V., Parekh, Kunal R., Smith, Casey
• Primary Examiner(s): HUBER, ROBERT T
• Application Number:
  US14/247,968
• Publication Number:
  US 20140217498A1
• Time in Patent Office: 959 Days
• Field of Search: 257/392, 257/532, 257/314, 257/E29.134, 257/E29.264
• US Class Current: 1/1
• CPC Class Codes: H01L 21/823425 manufacturing common source or drain regions between a plurality of conductor-insulator-semiconductor structures
• CPC Class Codes: H01L 21/82345 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/66621 using etching to form a recess at the gate location etching of semiconductor bodies H01L21/302
• CPC Class Codes: H01L 29/7831 with multiple gate structure FinFETs or MuGFETs H01L29/7855, thin film transistors H01L29/78645

Abstract

Recessed access transistor devices used with semiconductor devices may include gate electrodes having materials with multiple work functions, materials that are electrically isolated from each other and supplied with two or more voltage supplies, or materials that create a diode junction within the gate electrode.

Claims

1. A gate electrode, comprising:

a gate dielectric material overlying a bottom portion and sidewalls of a trench within a semiconductor substrate;

a first gate material in the trench and overlying the gate dielectric material over the bottom portion of the trench and overlying at least a portion of the gate dielectric material over the sidewalls of the trench, the first gate material having a first work function associated therewith, the first gate material comprising a P+ doped polysilicon material coupled to a first voltage supply;

a second gate material at least partially within the trench and overlying at least another portion of the gate dielectric material on the sidewalls, the second gate material having a second work function different from the first work function, the second gate material comprising a N+ doped polysilicon material coupled to a second voltage supply,

one of the first gate material and the second gate material configured to receive a first negative bias and the other of the first gate material and the second gate material configured to receive a second negative bias that is more negative than the first negative bias, the first gate material electrically isolated from the second gate material, the second gate material proximate a storage capacitor of a memory device and the first gate material proximate a bitline of the memory device,

wherein the gate dielectric material has a substantially uniform thickness from below the first gate material to a top surface of the second gate material; and

an insulator positioned between the first gate material and the second gate material, the insulator selected from the group consisting of silicon nitride and silicon dioxide and providing electrical isolation between the first gate material and the second gate material.

2. The gate electrode of claim 1, wherein the first gate material and the second gate material each contact the gate dielectric material.

3. The gate electrode of claim 1, wherein the second gate material comprises a material having a higher work function than a material of the first gate material.

4. The gate electrode of claim 1, wherein the first negative bias and the second negative bias originate from an access device driver.

5. The gate electrode of claim 1, wherein the first gate material vertically overlays the second gate material.

6. The gate electrode of claim 1, wherein an upper surface of the first gate material extends above an upper surface of an active region of the semiconductor substrate.

7. The gate electrode of claim 1, wherein each of the first gate material and the second gate material defines a nonplanar surface proximate the insulator, the nonplanar surface located at a laterally central portion of the first gate material and the second gate material.

8. The gate electrode of claim 1, wherein the insulator defines nonplanar upper and lower surfaces.

9. The gate electrode of claim 1, wherein the trench extends only in the semiconductor substrate.

10. The gate electrode of claim 1, wherein a laterally central portion of each of the first gate material and the second gate material comprises a nonplanar surface.

11. The gate electrode of claim 1, further comprising active areas comprising source and drain regions at a top portion of the semiconductor substrate and located above portions of the first gate material and the second gate material.

12. The gate electrode of claim 1, further comprising active areas comprising source and drain regions, the first gate material and the second gate material electrically isolated from the active areas at least by the gate dielectric material.