Semiconductor device and method for manufacturing the same

• US 9,502,553 B2
• Filed: 07/01/2015
• Issued: 11/22/2016
• Est. Priority Date: 04/30/2009
• Status: Active Grant

• Current Assignee: Mitsubishi Electric Corporation
• Original Assignee: Mitsubishi Electric Corporation
• Inventors: Miura, Naruhisa, Nakata, Shuhei, Ohtsuka, Kenichi, Watanabe, Shoyu, Yutani, Naoki
• Primary Examiner(s): YUSHINA, GALINA G
• Application Number:
  US14/789,364
• Publication Number:
  US 20150303297A1
• Time in Patent Office: 510 Days
• US Class Current: 1/1
• CPC Class Codes: H01L 23/53209 based on metals, e.g. alloys, metal silicides H01L23/53285 takes precedence
• CPC Class Codes: H01L 29/0611 for increasing or controlling the breakdown voltage of reverse biased devices H01L29/0661 takes precedence
• CPC Class Codes: H01L 29/0615 by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] LDD or drain offset regions H01L29/7833
• CPC Class Codes: H01L 29/0638 for preventing surface leakage due to surface inversion layer, e.g. with channel stopper channel stoppers in combination with isolation region for integrated circuits H01L21/762
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 29/42372 characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out H01L29/42324 takes precedence
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/45 Ohmic electrodes
• CPC Class Codes: H01L 29/4916 the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/4941 with a barrier layer between the silicon and the metal or metal silicide upper layer, e.g. Silicide/TiN/Polysilicon
• CPC Class Codes: H01L 29/4975 being a silicide layer, e.g. TiSi2
• CPC Class Codes: H01L 29/66068 the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
• CPC Class Codes: H01L 29/7805 in antiparallel, e.g. freewheel diode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

In a cell region of a first major surface of a semiconductor substrate of a first conductivity type, a first well of a second conductivity type is in an upper surface. A diffusion region of a first conductivity type is in the upper surface in the first well. A first gate insulating film is on the first well, and a first gate electrode on the first gate insulating film. A second well of a second conductivity type is in the upper surface of the first major surface on a peripheral portion of the cell region. A second gate insulating film is on the second well, and a thick field oxide film is on the peripheral side of the second gate insulating film. A second gate electrode is sequentially on the second gate insulating film and the field oxide film and electrically connected to the first gate electrode. A first electrode is connected to the first well, the second well and the diffusion region. A second electrode is connected on a second major surface of the semiconductor substrate. A gate wiring is on the field oxide film, going around a periphery of the cell region, and electrically connected to the second gate electrode. The gate wiring is a silicide of a constituting substance of the second gate electrode.

Claims

1. A semiconductor device comprising:

a semiconductor substrate having a first major surface and a second major surface facing each other;

a drift layer of a first conductivity type on the first major surface;

a first well of a second conductivity type in an upper portion of the drift layer disposed in a center of the semiconductor device;

a diffusion layer of a first conductivity type in an upper portion of the first well;

a second well of a second conductivity type in another upper portion of the drift layer disposed in a peripheral region of the semiconductor device;

a first electrode disposed above the first major surface of the semiconductor substrate and electrically connected to the first well and the second well;

a second electrode under the second major surface of the semiconductor substrate;

a first gate insulating film on the first well, a second gate insulating film on the second well;

a field oxide film on the second well;

a gate electrode on the second gate insulating film and the field oxide film; and

a gate wiring film including a silicide and disposed on the field oxide film;

wherein

a bottom surface of the gate wiring contacts a top surface of the field oxide; and

the gate wiring contacts a side portion of the gate electrode disposed further from the center of the semiconductor device.

2. The semiconductor device according to claim 1, further comprising:

an interlayer insulating film disposed on the gate electrode,

wherein the gate wiring is further disposed under the interlayer insulating film.

3. The semiconductor device according to claim 1, further comprising:

a gate pad including metal and electrically connected to the gate wiring.

4. The semiconductor device according to claim 1, wherein the gate wiring extends outwardly away from the gate electrode.

5. The semiconductor device according to claim 1, wherein the gate wiring includes Ni.

6. The semiconductor device according to claim 1, wherein the gate wiring is self-aligned.

7. The semiconductor device according to claim 1, wherein:

the drift layer has a first impurity concentration in a first range of 1×

10¹³ cm<sup>−

3</sup> to 1×

10¹⁸ cm<sup>−

3</sup>;

the second well has a second impurity concentration in a second range of 1×

10¹⁵ cm<sup>−

3</sup> to 1×

10¹⁹ cm<sup>−

3</sup>; and

the first impurity concentration exceeds the second impurity concentration only in the vicinity of an outer surface of the drift layer.

8. The semiconductor device according to claim 1, wherein the gate electrode includes poly-silicon.

9. The semiconductor device according to claim 1, wherein the semiconductor substrate and the drift layer are SiC.

10. A semiconductor device comprising:

a semiconductor substrate having a first major surface and a second major surface facing each other;

a drift layer of a first conductivity type on the first major surface;

a first well of a second conductivity type in an upper portion of the drift layer disposed in a center of the semiconductor device;

a diffusion layer of a first conductivity type in an upper portion of the first well;

a second well of a second conductivity type in another upper portion of the drift layer disposed in a peripheral region of the semiconductor device;

a first electrode above the first major surface of the semiconductor substrate and electrically connected to the first well and the second well;

a second electrode under the second major surface of the semiconductor substrate;

a first gate insulating film on the first well;

a second gate insulating film on the second well;

a field oxide film on the second well,

a gate electrode on the second gate insulating film and the field oxide film;

an interlayer insulating film disposed on the gate electrode and having a contact hole; and

a gate wiring including a silicide and disposed on an the field oxide film at a bottom of the contact hole of the interlayer insulating film;

wherein the gate wiring is further disposed under the interlayer insulating film.

11. The semiconductor device according to claim 10, further comprising:

a gate pad including metal and electrically connected to the gate wiring.

12. The semiconductor device according to claim 10, wherein the gate wiring extends outwardly away from the gate electrode.

13. The semiconductor device according to claim 10, wherein the gate wiring is connected to a side surface of the gate electrode.

14. The semiconductor device according to claim 10, wherein the gate wiring includes Ni.

15. The semiconductor device according to claim 10, wherein the gate wiring is self-aligned.

16. The semiconductor device according to claim 10, wherein the gate electrode includes poly-silicon.

17. The semiconductor device according to claim 10, wherein the semiconductor substrate and the drift layer are SiC.

18. The semiconductor device according to claim 10, wherein:

a width of the contact hole of the interlayer insulating film is 0.1 μ

m to 100 μ

m.

19. A semiconductor device comprising:

a semiconductor substrate having a first major surface and a second major surface facing each other;

a drift layer of a first conductivity type on the first major surface;

a first well of a second conductivity type in an upper portion of the drift layer disposed in a center of the semiconductor device;

a diffusion layer of a first conductivity type in an upper portion of the first well;

a second well of a second conductivity type in another upper portion of the drift layer disposed in a peripheral region of the semiconductor device;

a first electrode above the first major surface of the semiconductor substrate and electrically connected to the first well and the second well;

a second electrode under the second major surface of the semiconductor substrate;

a first gate insulating film on the first well;

a second gate insulating film on the second well;

a field oxide film on the second well;

a gate electrode on the second gate insulating film and the field oxide film;

an interlayer insulating film disposed on the gate electrode and having a contact hole; and

a gate wiring including a silicide and disposed on the field oxide film at a bottom of the contact hole of the interlayer insulating film;

wherein;

the drift layer has a first impurity concentration in a first range of 1×

10¹³ cm<sup>−

3</sup> to 1×

10¹⁸ cm<sup>−

3</sup>;

the second well has a second impurity concentration in a second range of 1×

10¹⁵ cm<sup>−

3</sup> to 1×

10¹⁹ cm<sup>−

3</sup>; and

the first impurity concentration exceeds the second impurity concentration only in the vicinity of an outer surface of the drift layer.